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📄 add25.rpt

📁 用CPLD控制LED、数码管的显示源代码
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-- Node name is 'ms2' = '|STATMACH:7|COUN2' 
-- Equation name is 'ms2', type is output 
 ms2     = TFFE( _EQ008,  _LC044, !clear,  VCC,  VCC);
  _EQ008 =  ms0 &  ms1;

-- Node name is 'ms3' = '|STATMACH:7|COUN3' 
-- Equation name is 'ms3', type is output 
 ms3     = DFFE( _EQ009 $  _LC040,  _LC044, !clear,  VCC,  VCC);
  _EQ009 =  _LC040 &  ms0 & !ms1 & !ms2 &  ms3;

-- Node name is 'OV' = '|STATMACH:4|:3' 
-- Equation name is 'OV', type is output 
 OV      = DFFE( _EQ010 $  GND, GLOBAL( clock), !clear,  VCC,  VCC);
  _EQ010 =  us0 & !us1 & !us2 &  us3;

-- Node name is 's0' = '|STATMACH:10|COUN0' 
-- Equation name is 's0', type is output 
 s0      = TFFE( VCC,  _LC061, !clear,  VCC,  VCC);

-- Node name is 's1' = '|STATMACH:10|COUN1' 
-- Equation name is 's1', type is output 
 s1      = DFFE( _EQ011 $  _LC048,  _LC061, !clear,  VCC,  VCC);
  _EQ011 =  _LC048 &  s0 & !s1 & !s2 &  s3;

-- Node name is 's2' = '|STATMACH:10|COUN2' 
-- Equation name is 's2', type is output 
 s2      = TFFE( _EQ012,  _LC061, !clear,  VCC,  VCC);
  _EQ012 =  s0 &  s1;

-- Node name is 's3' = '|STATMACH:10|COUN3' 
-- Equation name is 's3', type is output 
 s3      = DFFE( _EQ013 $  _LC029,  _LC061, !clear,  VCC,  VCC);
  _EQ013 =  _LC029 &  s0 & !s1 & !s2 &  s3;

-- Node name is 'us_hund0' = '|STATMACH:6|COUN0' 
-- Equation name is 'us_hund0', type is output 
 us_hund0 = TFFE( VCC,  _LC022, !clear,  VCC,  VCC);

-- Node name is 'us_hund1' = '|STATMACH:6|COUN1' 
-- Equation name is 'us_hund1', type is output 
 us_hund1 = DFFE( _EQ014 $  _LC042,  _LC022, !clear,  VCC,  VCC);
  _EQ014 =  _LC042 &  us_hund0 & !us_hund1 & !us_hund2 &  us_hund3;

-- Node name is 'us_hund2' = '|STATMACH:6|COUN2' 
-- Equation name is 'us_hund2', type is output 
 us_hund2 = TFFE( _EQ015,  _LC022, !clear,  VCC,  VCC);
  _EQ015 =  us_hund0 &  us_hund1;

-- Node name is 'us_hund3' = '|STATMACH:6|COUN3' 
-- Equation name is 'us_hund3', type is output 
 us_hund3 = DFFE( _EQ016 $  _LC043,  _LC022, !clear,  VCC,  VCC);
  _EQ016 =  _LC043 &  us_hund0 & !us_hund1 & !us_hund2 &  us_hund3;

-- Node name is 'us_ten0' = '|STATMACH:5|COUN0' 
-- Equation name is 'us_ten0', type is output 
 us_ten0 = TFFE( VCC,  OV, !clear,  VCC,  VCC);

-- Node name is 'us_ten1' = '|STATMACH:5|COUN1' 
-- Equation name is 'us_ten1', type is output 
 us_ten1 = DFFE( _EQ017 $  _LC031,  OV, !clear,  VCC,  VCC);
  _EQ017 =  _LC031 &  us_ten0 & !us_ten1 & !us_ten2 &  us_ten3;

-- Node name is 'us_ten2' = '|STATMACH:5|COUN2' 
-- Equation name is 'us_ten2', type is output 
 us_ten2 = TFFE( _EQ018,  OV, !clear,  VCC,  VCC);
  _EQ018 =  us_ten0 &  us_ten1;

-- Node name is 'us_ten3' = '|STATMACH:5|COUN3' 
-- Equation name is 'us_ten3', type is output 
 us_ten3 = DFFE( _EQ019 $  _LC032,  OV, !clear,  VCC,  VCC);
  _EQ019 =  _LC032 &  us_ten0 & !us_ten1 & !us_ten2 &  us_ten3;

-- Node name is 'us0' = '|STATMACH:4|COUN0' 
-- Equation name is 'us0', type is output 
 us0     = TFFE( VCC, GLOBAL( clock), !clear,  VCC,  VCC);

-- Node name is 'us1' = '|STATMACH:4|COUN1' 
-- Equation name is 'us1', type is output 
 us1     = DFFE( _EQ020 $  _LC030, GLOBAL( clock), !clear,  VCC,  VCC);
  _EQ020 =  _LC030 &  us0 & !us1 & !us2 &  us3;

-- Node name is 'us2' = '|STATMACH:4|COUN2' 
-- Equation name is 'us2', type is output 
 us2     = TFFE( _EQ021, GLOBAL( clock), !clear,  VCC,  VCC);
  _EQ021 =  us0 &  us1;

-- Node name is 'us3' = '|STATMACH:4|COUN3' 
-- Equation name is 'us3', type is output 
 us3     = DFFE( _EQ022 $  _LC023, GLOBAL( clock), !clear,  VCC,  VCC);
  _EQ022 =  _LC023 &  us0 & !us1 & !us2 &  us3;

-- Node name is '|STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC030', type is buried 
_LC030   = LCELL( us1 $  us0);

-- Node name is '|STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC023', type is buried 
_LC023   = LCELL( us3 $  _EQ023);
  _EQ023 =  us0 &  us1 &  us2;

-- Node name is '|STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC031', type is buried 
_LC031   = LCELL( us_ten1 $  us_ten0);

-- Node name is '|STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC032', type is buried 
_LC032   = LCELL( us_ten3 $  _EQ024);
  _EQ024 =  us_ten0 &  us_ten1 &  us_ten2;

-- Node name is '|STATMACH:5|:3' 
-- Equation name is '_LC022', type is buried 
_LC022   = DFFE( _EQ025 $  GND,  OV, !clear,  VCC,  VCC);
  _EQ025 =  us_ten0 & !us_ten1 & !us_ten2 &  us_ten3;

-- Node name is '|STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC042', type is buried 
_LC042   = LCELL( us_hund1 $  us_hund0);

-- Node name is '|STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC043', type is buried 
_LC043   = LCELL( us_hund3 $  _EQ026);
  _EQ026 =  us_hund0 &  us_hund1 &  us_hund2;

-- Node name is '|STATMACH:6|:3' 
-- Equation name is '_LC044', type is buried 
_LC044   = DFFE( _EQ027 $  GND,  _LC022, !clear,  VCC,  VCC);
  _EQ027 =  us_hund0 & !us_hund1 & !us_hund2 &  us_hund3;

-- Node name is '|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC047', type is buried 
_LC047   = LCELL( ms1 $  ms0);

-- Node name is '|STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC040', type is buried 
_LC040   = LCELL( ms3 $  _EQ028);
  _EQ028 =  ms0 &  ms1 &  ms2;

-- Node name is '|STATMACH:7|:3' 
-- Equation name is '_LC045', type is buried 
_LC045   = DFFE( _EQ029 $  GND,  _LC044, !clear,  VCC,  VCC);
  _EQ029 =  ms0 & !ms1 & !ms2 &  ms3;

-- Node name is '|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC063', type is buried 
_LC063   = LCELL( ms_ten1 $  ms_ten0);

-- Node name is '|STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC062', type is buried 
_LC062   = LCELL( ms_ten3 $  _EQ030);
  _EQ030 =  ms_ten0 &  ms_ten1 &  ms_ten2;

-- Node name is '|STATMACH:8|:3' 
-- Equation name is '_LC055', type is buried 
_LC055   = DFFE( _EQ031 $  GND,  _LC045, !clear,  VCC,  VCC);
  _EQ031 =  ms_ten0 & !ms_ten1 & !ms_ten2 &  ms_ten3;

-- Node name is '|STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC064', type is buried 
_LC064   = LCELL( ms_hund1 $  ms_hund0);

-- Node name is '|STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC056', type is buried 
_LC056   = LCELL( ms_hund3 $  _EQ032);
  _EQ032 =  ms_hund0 &  ms_hund1 &  ms_hund2;

-- Node name is '|STATMACH:9|:3' 
-- Equation name is '_LC061', type is buried 
_LC061   = DFFE( _EQ033 $  GND,  _LC055, !clear,  VCC,  VCC);
  _EQ033 =  ms_hund0 & !ms_hund1 & !ms_hund2 &  ms_hund3;

-- Node name is '|STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC048', type is buried 
_LC048   = LCELL( s1 $  s0);

-- Node name is '|STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC029', type is buried 
_LC029   = LCELL( s3 $  _EQ034);
  _EQ034 =  s0 &  s1 &  s2;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                  d:\7128slc84-15\add25.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 5,092K

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