📄 add25.rpt
字号:
69 54 D FF t 0 0 0 1 1 3 3 us_ten0 (|STATMACH:5|:12)
37 20 B FF t 0 0 0 1 6 3 3 us_ten1 (|STATMACH:5|:11)
29 27 B FF t 0 0 0 1 3 2 2 us_ten2 (|STATMACH:5|:10)
33 24 B FF t 0 0 0 1 6 2 2 us_ten3 (|STATMACH:5|:9)
75 59 D FF + t 0 0 0 1 0 4 2 us0 (|STATMACH:4|:12)
28 28 B FF + t 0 0 0 1 5 4 2 us1 (|STATMACH:4|:11)
39 19 B FF + t 0 0 0 1 2 3 1 us2 (|STATMACH:4|:10)
36 21 B FF + t 0 0 0 1 5 3 1 us3 (|STATMACH:4|:9)
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\7128slc84-15\add25.rpt
add25
** BURIED LOGIC **
Shareable
Expanders Fan-In Fan-Out
Pin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name
(25) 30 B SOFT t 0 0 0 0 2 1 0 |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(34) 23 B SOFT t 0 0 0 0 4 1 0 |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(24) 31 B SOFT t 0 0 0 0 2 1 0 |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(23) 32 B SOFT t 0 0 0 0 4 1 0 |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(35) 22 B DFFE t 0 0 0 1 5 4 1 |STATMACH:5|:3
(55) 42 C SOFT t 0 0 0 0 2 1 0 |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(56) 43 C SOFT t 0 0 0 0 4 1 0 |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(57) 44 C DFFE t 0 0 0 1 5 4 1 |STATMACH:6|:3
(61) 47 C SOFT t 0 0 0 0 2 1 0 |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(52) 40 C SOFT t 0 0 0 0 4 1 0 |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(58) 45 C DFFE t 0 0 0 1 5 4 1 |STATMACH:7|:3
(80) 63 D SOFT t 0 0 0 0 2 1 0 |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(79) 62 D SOFT t 0 0 0 0 4 1 0 |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(70) 55 D DFFE t 0 0 0 1 5 4 1 |STATMACH:8|:3
(81) 64 D SOFT t 0 0 0 0 2 1 0 |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(71) 56 D SOFT t 0 0 0 0 4 1 0 |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
(77) 61 D DFFE t 0 0 0 1 5 4 0 |STATMACH:9|:3
(62) 48 C SOFT t 0 0 0 0 2 1 0 |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
(27) 29 B SOFT t 0 0 0 0 4 1 0 |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: d:\7128slc84-15\add25.rpt
add25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC17 OV
| +----------------------------- LC30 |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | +--------------------------- LC23 |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | +------------------------- LC31 |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | +----------------------- LC32 |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | +--------------------- LC22 |STATMACH:5|:3
| | | | | | +------------------- LC29 |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC18 s1
| | | | | | | | +--------------- LC25 s2
| | | | | | | | | +------------- LC26 s3
| | | | | | | | | | +----------- LC20 us_ten1
| | | | | | | | | | | +--------- LC27 us_ten2
| | | | | | | | | | | | +------- LC24 us_ten3
| | | | | | | | | | | | | +----- LC28 us1
| | | | | | | | | | | | | | +--- LC19 us2
| | | | | | | | | | | | | | | +- LC21 us3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC17 -> - - - - - * - - - - * * * - - - | - * - * | <-- OV
LC30 -> - - - - - - - - - - - - - * - - | - * - - | <-- |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC23 -> - - - - - - - - - - - - - - - * | - * - - | <-- |STATMACH:4|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC31 -> - - - - - - - - - - * - - - - - | - * - - | <-- |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC32 -> - - - - - - - - - - - - * - - - | - * - - | <-- |STATMACH:5|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC29 -> - - - - - - - - - * - - - - - - | - * - - | <-- |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC18 -> - - - - - - * * * * - - - - - - | - * * - | <-- s1
LC25 -> - - - - - - * * * * - - - - - - | - * - - | <-- s2
LC26 -> - - - - - - * * - * - - - - - - | - * - - | <-- s3
LC20 -> - - - * * * - - - - * * * - - - | - * - - | <-- us_ten1
LC27 -> - - - - * * - - - - * * * - - - | - * - - | <-- us_ten2
LC24 -> - - - - * * - - - - * - * - - - | - * - - | <-- us_ten3
LC28 -> * * * - - - - - - - - - - * * * | - * - - | <-- us1
LC19 -> * - * - - - - - - - - - - * * * | - * - - | <-- us2
LC21 -> * - * - - - - - - - - - - * - * | - * - - | <-- us3
Pin
22 -> * - - - - * - * * * * * * * * * | - * * * | <-- clear
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- clock
LC61 -> - - - - - - - * * * - - - - - - | - * * - | <-- |STATMACH:9|:3
LC48 -> - - - - - - - * - - - - - - - - | - * - - | <-- |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC33 -> - - - - - - * * * * - - - - - - | - * * - | <-- s0
LC54 -> - - - * * * - - - - * * * - - - | - * - - | <-- us_ten0
LC59 -> * * * - - - - - - - - - - * * * | - * - - | <-- us0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\7128slc84-15\add25.rpt
add25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC38 ms0
| +----------------------------- LC37 ms1
| | +--------------------------- LC36 ms2
| | | +------------------------- LC34 ms3
| | | | +----------------------- LC42 |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | | +--------------------- LC43 |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | | +------------------- LC44 |STATMACH:6|:3
| | | | | | | +----------------- LC47 |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | | | | | +--------------- LC40 |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | +------------- LC45 |STATMACH:7|:3
| | | | | | | | | | +----------- LC48 |STATMACH:10|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | +--------- LC33 s0
| | | | | | | | | | | | +------- LC41 us_hund0
| | | | | | | | | | | | | +----- LC46 us_hund1
| | | | | | | | | | | | | | +--- LC35 us_hund2
| | | | | | | | | | | | | | | +- LC39 us_hund3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC38 -> * * * * - - - * * * - - - - - - | - - * - | <-- ms0
LC37 -> - * * * - - - * * * - - - - - - | - - * - | <-- ms1
LC36 -> - * * * - - - - * * - - - - - - | - - * - | <-- ms2
LC34 -> - * - * - - - - * * - - - - - - | - - * - | <-- ms3
LC42 -> - - - - - - - - - - - - - * - - | - - * - | <-- |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC43 -> - - - - - - - - - - - - - - - * | - - * - | <-- |STATMACH:6|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC44 -> * * * * - - - - - * - - - - - - | - - * - | <-- |STATMACH:6|:3
LC47 -> - * - - - - - - - - - - - - - - | - - * - | <-- |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC40 -> - - - * - - - - - - - - - - - - | - - * - | <-- |STATMACH:7|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC33 -> - - - - - - - - - - * * - - - - | - * * - | <-- s0
LC41 -> - - - - * * * - - - - - * * * * | - - * - | <-- us_hund0
LC46 -> - - - - * * * - - - - - - * * * | - - * - | <-- us_hund1
LC35 -> - - - - - * * - - - - - - * * * | - - * - | <-- us_hund2
LC39 -> - - - - - * * - - - - - - * - * | - - * - | <-- us_hund3
Pin
22 -> * * * * - - * - - * - * * * * * | - * * * | <-- clear
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- clock
LC22 -> - - - - - - * - - - - - * * * * | - - * - | <-- |STATMACH:5|:3
LC61 -> - - - - - - - - - - - * - - - - | - * * - | <-- |STATMACH:9|:3
LC18 -> - - - - - - - - - - * - - - - - | - * * - | <-- s1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\7128slc84-15\add25.rpt
add25
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC52 ms_hund0
| +----------------------------- LC60 ms_hund1
| | +--------------------------- LC53 ms_hund2
| | | +------------------------- LC58 ms_hund3
| | | | +----------------------- LC57 ms_ten0
| | | | | +--------------------- LC51 ms_ten1
| | | | | | +------------------- LC50 ms_ten2
| | | | | | | +----------------- LC49 ms_ten3
| | | | | | | | +--------------- LC63 |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | +------------- LC62 |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | +----------- LC55 |STATMACH:8|:3
| | | | | | | | | | | +--------- LC64 |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
| | | | | | | | | | | | +------- LC56 |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
| | | | | | | | | | | | | +----- LC61 |STATMACH:9|:3
| | | | | | | | | | | | | | +--- LC54 us_ten0
| | | | | | | | | | | | | | | +- LC59 us0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC52 -> * * * * - - - - - - - * * * - - | - - - * | <-- ms_hund0
LC60 -> - * * * - - - - - - - * * * - - | - - - * | <-- ms_hund1
LC53 -> - * * * - - - - - - - - * * - - | - - - * | <-- ms_hund2
LC58 -> - * - * - - - - - - - - * * - - | - - - * | <-- ms_hund3
LC57 -> - - - - * * * * * * * - - - - - | - - - * | <-- ms_ten0
LC51 -> - - - - - * * * * * * - - - - - | - - - * | <-- ms_ten1
LC50 -> - - - - - * * * - * * - - - - - | - - - * | <-- ms_ten2
LC49 -> - - - - - * - * - * * - - - - - | - - - * | <-- ms_ten3
LC63 -> - - - - - * - - - - - - - - - - | - - - * | <-- |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC62 -> - - - - - - - * - - - - - - - - | - - - * | <-- |STATMACH:8|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
LC55 -> * * * * - - - - - - - - - * - - | - - - * | <-- |STATMACH:8|:3
LC64 -> - * - - - - - - - - - - - - - - | - - - * | <-- |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node1
LC56 -> - - - * - - - - - - - - - - - - | - - - * | <-- |STATMACH:9|LPM_ADD_SUB:58|addcore:adder|addcore:adder0|result_node3
Pin
22 -> * * * * * * * * - - * - - * * * | - * * * | <-- clear
83 -> - - - - - - - - - - - - - - - - | - - - - | <-- clock
LC17 -> - - - - - - - - - - - - - - * - | - * - * | <-- OV
LC45 -> - - - - * * * * - - * - - - - - | - - - * | <-- |STATMACH:7|:3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\7128slc84-15\add25.rpt
add25
** EQUATIONS **
clear : INPUT;
clock : INPUT;
-- Node name is 'ms_hund0' = '|STATMACH:9|COUN0'
-- Equation name is 'ms_hund0', type is output
ms_hund0 = TFFE( VCC, _LC055, !clear, VCC, VCC);
-- Node name is 'ms_hund1' = '|STATMACH:9|COUN1'
-- Equation name is 'ms_hund1', type is output
ms_hund1 = DFFE( _EQ001 $ _LC064, _LC055, !clear, VCC, VCC);
_EQ001 = _LC064 & ms_hund0 & !ms_hund1 & !ms_hund2 & ms_hund3;
-- Node name is 'ms_hund2' = '|STATMACH:9|COUN2'
-- Equation name is 'ms_hund2', type is output
ms_hund2 = TFFE( _EQ002, _LC055, !clear, VCC, VCC);
_EQ002 = ms_hund0 & ms_hund1;
-- Node name is 'ms_hund3' = '|STATMACH:9|COUN3'
-- Equation name is 'ms_hund3', type is output
ms_hund3 = DFFE( _EQ003 $ _LC056, _LC055, !clear, VCC, VCC);
_EQ003 = _LC056 & ms_hund0 & !ms_hund1 & !ms_hund2 & ms_hund3;
-- Node name is 'ms_ten0' = '|STATMACH:8|COUN0'
-- Equation name is 'ms_ten0', type is output
ms_ten0 = TFFE( VCC, _LC045, !clear, VCC, VCC);
-- Node name is 'ms_ten1' = '|STATMACH:8|COUN1'
-- Equation name is 'ms_ten1', type is output
ms_ten1 = DFFE( _EQ004 $ _LC063, _LC045, !clear, VCC, VCC);
_EQ004 = _LC063 & ms_ten0 & !ms_ten1 & !ms_ten2 & ms_ten3;
-- Node name is 'ms_ten2' = '|STATMACH:8|COUN2'
-- Equation name is 'ms_ten2', type is output
ms_ten2 = TFFE( _EQ005, _LC045, !clear, VCC, VCC);
_EQ005 = ms_ten0 & ms_ten1;
-- Node name is 'ms_ten3' = '|STATMACH:8|COUN3'
-- Equation name is 'ms_ten3', type is output
ms_ten3 = DFFE( _EQ006 $ _LC062, _LC045, !clear, VCC, VCC);
_EQ006 = _LC062 & ms_ten0 & !ms_ten1 & !ms_ten2 & ms_ten3;
-- Node name is 'ms0' = '|STATMACH:7|COUN0'
-- Equation name is 'ms0', type is output
ms0 = TFFE( VCC, _LC044, !clear, VCC, VCC);
-- Node name is 'ms1' = '|STATMACH:7|COUN1'
-- Equation name is 'ms1', type is output
ms1 = DFFE( _EQ007 $ _LC047, _LC044, !clear, VCC, VCC);
_EQ007 = _LC047 & ms0 & !ms1 & !ms2 & ms3;
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -