cache.c

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	cache.c (SH7727)
 *	Cache Operation
 */

#include <basic.h>
#include <tk/tkernel.h>

/*
 * Size of cache per way
 */
#define CACHESIZE	0x1000U

/*
 * Flush 1 way cache
 *	Flush 1 page of cache (4 KB) including the address specified 
 *	by the logical address 'laddr.'
 *
 *	Execute cache control using the shadow image in P2 area because
 *	the program must be in the non-cache area.
 *	Therefore do not call "_flush_cache_" directly.
 *	Call by the address stored in '_FlushCacheP2_.'
 */
LOCAL void _flush_cache_( VP laddr )
{
	register UW	ent	asm("r1");
	register UW	tag	asm("r2");

	tag = (UW)laddr & 0x1ffff000;
	for ( ent = 0x000; ent < 0x1000; ent += 0x010 ) {
		*(_UW*)(0xf0000008 | ent) = (tag | ent) & 0xfffffc00;
	}
}

LOCAL FP _FlushCacheP2_ = (FP)((UW)&_flush_cache_ + 0x20000000);

#define FlushCacheP2(laddr)	(*_FlushCacheP2_)(laddr)

/*
 * Cache flush
 *	Flush cache between 'laddr' and 'len' bytes areas.
 *	Writeback and disable cache
 */
EXPORT void FlushCache( VP laddr, INT len )
{
	B	*top, *end;
	UINT	imask;

	top = (B*)((UW)laddr & ~(CACHESIZE-1));
	end = (B*)laddr + len;

	while ( top < end ) {

		DI(imask);
		FlushCacheP2(top);
		EI(imask);

		top += CACHESIZE;
	}
}

EXPORT void FlushCacheM( VP laddr, INT len, UINT mode )
{
	/* Ignore 'mode', because of unified cache,
	   which stores both instructions and data */
	FlushCache(laddr, len);
}