📄 tkdev_conf.h
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/* *---------------------------------------------------------------------- * T-Kernel * * Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved. * T-Kernel is distributed under the T-License. *---------------------------------------------------------------------- * * Version: 1.02.02 * Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9. * *---------------------------------------------------------------------- *//* * tkdev_conf.h (S1C38K) * Target System Configuration */#ifndef _TKDEV_CONF_#define _TKDEV_CONF_/* Also included from assembler source *//* * Timer */#define TM1_IRQ 5 /* Timer #1 IRQ number */#define VECNO_TM1 ( EIT_IRQ(TM1_IRQ) ) /* Timer #1 interrupt vector number */#define TMR(n) ( 0xf8000080 + (n) ) /* Timer I/O address */#define TM1_LOAD TMR(0x20) /* RW: Load register */#define TM1_COUNT TMR(0x24) /* R-: Count register */#define TM1_CTRL TMR(0x28) /* RW: Control register */#define TM1_INTCLR TMR(0x2c) /* -W: Interrupt clear */#define TM_INTREQ TMR(0x78) /* R-: Interrupt request flag */#define TM_SEL TMR(0x7c) /* RW: Timer select register */ /* TM_SEL setting value */#define TM_SEL1 0x00 /* Select timer #1 */ /* TM1_CTRL setting value */#define TMC_ENA 0x80U /* Timer operation */#define TMC_FREE 0x00U /* Free-running mode */#define TMC_CYC 0x40U /* Cyclic mode */#define TMC_SINGL 0x60U /* Single mode */#define TMC_DIV1 0x00U /* Do not divide */#define TMC_DIV16 0x04U /* 16 dividing */#define TMC_DIV256 0x08U /* 256 dividing */#define TMC_DIV4 0x10U /* 4 dividing */#define TMC_DIV8 0x14U /* 8 dividing */#define TMC_DIV32 0x18U /* 32 dividing */#define TMC_RELOAD 0x02U /* re-load */#define TMC_INT 0x01U /* Interrupt request (Read Only) */#define TMCLK 24 /* Timer clock input (MHz) *//* * Timer interrupt level * Because there is no interrupt priority function in 'S1C38000', * it is not meaningful. */#define TIMER_INTLEVEL 0#endif /* _TKDEV_CONF_ */
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