icrt0.s

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	icrt0.S (M32104)
 *	System Startup
 */

#include <machine.h>
#include <tk/sysdef.h>
#include <tk/asm.h>

#if _Csym == 0
#define	START	_start
#else
#define	START	start
#endif

	/* Low level memory manager information */
	.comm	Csym(lowmem_top), 4	// Head of area (Low address)
	.comm	Csym(lowmem_limit), 4	// End of area (High address)

#define	SYSINFO		0x006001d0	// System common information
#define	RAM_TOP		(SYSINFO + 8)	// Head of ext. RAM free area
#define	RAM_END		(SYSINFO + 12)	// End of ext. RAM free area

	.text
	.balign	4
	.globl	START
	.type	START, @function
START:
	/* Use the stack set by the monitor */

	ldi	r0, #PSW_SM		// PSW initial setting 
	mvtc	r0, psw			// SM=1 IE=0

	bl	cache_on		// Cache on

	seth	r1, #shigh(__data_org)	// Initialization of 'data' area
	add3	r1, r1, #low(__data_org)
	seth	r2, #shigh(__data_start)
	add3	r2, r2, #low(__data_start)
	beq	r1, r2, nocopy_data
	seth	r3, #shigh(_edata)
	add3	r3, r3, #low(_edata)
	beq	r2, r3, nocopy_data
	addi	r2, #-4
	addi	r3, #-4
  copy_data:
	ld	r0, @r1+
	st	r0, @+r2
	bne	r2, r3, copy_data
  nocopy_data:

	ldi	r0, #0			// Clear 'bss' area
	seth	r1, #shigh(__bss_start - 4)
	add3	r1, r1, #low(__bss_start - 4)
	seth	r2, #shigh(_end - 4)
	add3	r2, r2, #low(_end - 4)
	beq	r1, r2, nobss
  clrbss:
	st	r0, @+r1
	bne	r1, r2, clrbss
  nobss:

	seth	r1, #shigh(_end)	// Low level memory manager initial setting
	add3	r0, r1, #low(_end)
	seth	r1, #shigh(RAM_TOP)
	ld	r1, @(low(RAM_TOP), r1)
	cmpu	r1, r0			// _end or RAM_TOP
	bc	l1			// Either of High addresses
	mv	r0, r1
  l1:
	seth	r2, #CsymH(lowmem_top)
	st	r0, @(CsymL(lowmem_top), r2)	// lowmem_top = _end or RAM_TOP
	seth	r1, #shigh(RAM_END)
	ld	r0, @(low(RAM_END), r1)
	seth	r2, #CsymH(lowmem_limit)
	st	r0, @(CsymL(lowmem_limit), r2)	// lowmem_limit = RAM_END

	bl	Csym(main)		// System startup

  l_end:				// Not suppose to return from 'main,'
	bra	l_end			// but, just in case, prepare for out of control.


/*
 * Non-cache area setting value
 */
#define	DNCR1_SETUP	( 0x00600000 | CC_NCSZ_2MB )
#define	DNCR2_SETUP	( 0x01000000 | CC_NCSZ_16MB )
#define	DNCR3_SETUP	( 0x02000000 | CC_NCSZ_32MB )

/*
 * Cache on
 */
	.text
	.balign	4
cache_on:
	ldi	r0, #0			// Disable cache once.
	ldi	r1, #CC_DCB | CC_DIV | CC_IIV
	st	r1, @(slow(CC_MCCR), r0)

	ldi	r1, #CC_NCSZ_NONE	// No non-instruction cache area
	st	r1, @(slow(CC_INCR1), r0)
	st	r1, @(slow(CC_INCR2), r0)

	seth	r1, #high(DNCR1_SETUP)	// Set non-data cache area 1
	or3	r1, r1, #low(DNCR1_SETUP)
	st	r1, @(slow(CC_DNCR1), r0)

	seth	r1, #high(DNCR2_SETUP)	// Set non-data cache area 2
	or3	r1, r1, #low(DNCR2_SETUP)
	st	r1, @(slow(CC_DNCR2), r0)

	seth	r1, #high(DNCR3_SETUP)	// Set non-data cache area 3
	or3	r1, r1, #low(DNCR3_SETUP)
	st	r1, @(slow(CC_DNCR3), r0)

	ldi	r1, #CC_DCM | CC_ICM	// Enable cache
	st	r1, @(slow(CC_MCCR), r0)

	jmp	lr