syslib_depend.h

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)syslib_depend.h (tk/SH7727)
 *
 *	T-Kernel/SM SH7727 Library
 */

#ifndef __TK_SYSLIB_DEPEND_H__
#define __TK_SYSLIB_DEPEND_H__

#ifdef __cplusplus
extern "C" {
#endif

/*
 * CPU interrupt control
 *	'intsts' is the value of SR register in CPU
 *	disint()  Set SR.I = 15 and return the original SR to the return value.
 *	enaint()  Set SR.I = intsts.I. Do not change except for SR.I.
 *		  Return the original SR to the return value.
 */
IMPORT UINT disint( void );
IMPORT UINT enaint( UINT intsts );
#define DI(intsts)	( (intsts) = disint() )
#define EI(intsts)	( enaint(intsts) )
#define isDI(intsts)	( ((intsts) & 0x00f0) != 0 )

/*
 * Enable the higher level of interrupt than intlevel (0-15)
 *	Set 'intlevel' to SR.I in CPU.
 *	Return the original SR to the return value.
 *	Use when enabling a multiplexed interrupt in interrupt handler.
 */
#define SetIntLevel(intlevel)	( enaint((intlevel) << 4) )

/*
 * Request the interrupt level (1-15) by the value of INTEVT (0x200-0x3c0)
 */
#define IntLevel(intevt)	( 0x1f - ((intevt) >> 5) )

/*
 * Interrupt vector
 *	Interrupt vector is the value of the interrupt factor code INTVEC 2
 */
typedef UINT	INTVEC;

/* Convert to the interrupt definition number */
#define DINTNO(intvec)	(intvec)

/*
 * Interrupt vector value (part)
 */
typedef enum intvec {
	IV_NMI		= 0x1c0,
	IV_IRQ0		= 0x3a0,	/* IRL: 2 */
	IV_IRQ1		= 0x320,	/* IRL: 6 */
	IV_IRQ2		= 0x2a0,	/* IRL:10 */
	IV_IRQ3		= 0x220,	/* IRL:14 */
	IV_IRQ4		= 0x680,	/* IRQ */
	IV_IRQ5		= 0x6a0,
	IV_PINT0	= 0x700,	/* PINT0-7  */
	IV_PINT8	= 0x720,	/* PINT8-15 */
	IV_ERI2		= 0x900,	/* SCIF */
	IV_RXI2		= 0x920,
	IV_BRI2		= 0x940,
	IV_TXI2		= 0x960,
	IV_USBHI	= 0xa00		/* USBH */
} IntVec;

typedef enum irq {
	IRQ0		= 0,
	IRQ1		= 1,
	IRQ2		= 2,
	IRQ3		= 3,
	IRQ4		= 4,
	IRQ5		= 5
} IRQ;

/*
 * Mutual conversion between IRQ and INTVEC
 */
#define INTVECNO(irq)	( ((irq) < 4) ? \
				( 0x3a0 - ((irq) << 7) ) : \
				( 0x600 + ((irq) << 5) ) )
#define IRQNO(vec)	( ((vec) < 0x600) ? \
				( (0x3a0 - (vec)) >> 7 ) : \
				( ((vec) - 0x600) >> 5 ) )

/*
 * Interrupt controller control
 *	Need to execute interrupt clear for interrupt controller
 *	with interrupt handleronly on the edge trigger mode.
 *	Edge trigger is available only for IRQ4-5.
 *	Do not need interrupt clear on the level trigger mode
 *	even for IRQ4-5.
 *
 *	Only IV_IRQ4 - IV_IRQ5 can be specified by 'intvec.'
 */
IMPORT void ClearInt( INTVEC intvec );	/* Clear Interrupt IRQ */

/*
 * Issue EOI(End Of Interrupt)
 */
#define EndOfInt(intvec)

/* ------------------------------------------------------------------------ */

/*
 * I/O port access
 *	Only memory mapped I/O for SH
 */
Inline void out_w( INT port, UW data )
{
	Asm("mov.l %0, @%1":: "r"(data), "r"(port));
}
Inline void out_h( INT port, UH data )
{
	Asm("mov.w %0, @%1":: "r"(data), "r"(port));
}
Inline void out_b( INT port, UB data )
{
	Asm("mov.b %0, @%1":: "r"(data), "r"(port));
}

Inline UW in_w( INT port )
{
	UW	data;
	Asm("mov.l @%1, %0": "=r"(data): "r"(port));
	return data;
}
Inline UH in_h( INT port )
{
	UH	data;
	/* Compensation for PC card I/O */
	if ( ((UINT)port & 0xfffc0000U) == 0xb8240000U
	  || ((UINT)port & 0xff3c0000U) == 0xb6240000U ) {
		port -= 0x40000;
	}
	Asm("mov.w @%1, %0": "=r"(data): "r"(port));
	return data;
}
Inline UB in_b( INT port )
{
	UB	data;
	Asm("mov.b @%1, %0": "=r"(data): "r"(port));
	return data;
}

#ifdef __cplusplus
}
#endif
#endif /* __TK_SYSLIB_DEPEND_H__ */