sysdef_depend.h

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)sysdef_depend.h (tk/SH7727)
 *
 *	Definition about SH7727
 *
 *	Included also from assembler program.
 */

#ifndef __TK_SYSDEF_DEPEND_H__
#define __TK_SYSDEF_DEPEND_H__

/*
 * Use specify register
 */
#define SP	r15	/* Stack pointer */

/*
 * BANK1 register
 *	R0	For work				With task
 *	R1	Reservation				With task
 *	R2 MDR	Operation mode register		  	With task
 *	R3 SST	System stack top		  	With task
 *	R4	For work				Task independent
 *	R5	Reservation				Task independent
 *	R6 ISP	EIT stack pointer	  		Task independent
 *	R7	For EIT work				Task independent
 *		(Available only at SR.BL=1)
 */
#define MDR	r2	/* Operation mode register */
#define SST	r3	/* System stack top */
#define ISP	r6	/* EIT stack pointer */

/*
 * MDR register
 */
#define MDR_DCT		0x80000000	/* Delayed context trap request */
#define MDR_PPL(n)	( (n) << 16 )	/* Previous protection level (0-3) */
#define MDR_CPL(n)	( (n) )		/* Current protection level (0-3) */

/*
 * SR register
 */
#define SR_MD		0x40000000	/* Privilege mode */
#define SR_RB		0x20000000	/* Register bank */
#define SR_BL		0x10000000	/* Interrupt block */
#define SR_DSP		0x00001000	/* DSP arithmetic mode */
#define SR_I(n)		( (n) << 4 )	/* Interrupt mask register (0-15) */

/*
 * EIT register
 */
#define TRA		0xffffffd0	/* W:TRAPA number */
#define EXPEVT		0xffffffd4	/* W:Exception factor */
#define INTEVT		0xffffffd8	/* W:Interrupt factor */
#define INTEVT2		0xa4000000	/* W:Interrupt factor 2 */

/*
 * MMU register
 */
#define PTEH		0xfffffff0	/* W:Page table entry upper */
#define PTEL		0xfffffff4	/* W:Page table entry lower */
#define TTB		0xfffffff8	/* W:Page table base */
#define TEA		0xfffffffc	/* W:TLB exception address */
#define MMUCR		0xffffffe0	/* W:MMU control */

#define MMU_AT		0x00000001	/* MMU enable */
#define MMU_IX		0x00000002	/* Index mode */
#define MMU_TF		0x00000004	/* TLB flush */
#define MMU_RC		0x00000030	/* Random counter */
#define MMU_SV		0x00000100	/* Single virtual memory mode */

/*
 * Cache register
 */
#define CCR		0xffffffec	/* W:Cache control */
#define CCR2		0xa40000b0	/* W:Cache control 2 */

#define CCR_CE		0x00000001	/* Cache enable */
#define CCR_WT		0x00000002	/* Write through (U0 P0 P3 area) */
#define CCR_CB		0x00000004	/* Write back (P1 area) */
#define CCR_CF		0x00000008	/* Cache flush */

/*
 * Interrupt controller
 */
#define ICR0		0xfffffee0	/* H:Interrupt control 0 */
#define ICR1		0xa4000010	/* H:Interrupt control 1 */
#define ICR2		0xa4000012	/* H:Interrupt control 2 */
#define ICR3		0xa4000228	/* H:Interrupt control 3 */
#define PINTER		0xa4000014	/* H:PINT Interrupt enable */
#define IPRA		0xfffffee2	/* H:Interrupt priority setting A */
#define IPRB		0xfffffee4	/* H:Interrupt priority setting B */
#define IPRC		0xa4000016	/* H:Interrupt priority setting C */
#define IPRD		0xa4000018	/* H:Interrupt priority setting D */
#define IPRE		0xa400001a	/* H:Interrupt priority setting E */
#define IPRF		0xa4000220	/* H:Interrupt priority setting F */
#define IPRG		0xa4000222	/* H:Interrupt priority setting G */
#define IRR0		0xa4000004	/* B:Interrupt request 0 */
#define IRR1		0xa4000006	/* B:Interrupt request 1 */
#define IRR2		0xa4000008	/* B:Interrupt request 2 */
#define IRR3		0xa4000224	/* H:Interrupt request 3 */
#define IRR4		0xa4000226	/* H:Interrupt request 4 */

/*
 * Interrupt vector number for T-Monitor
 */
#define TRAP_MONITOR	0x70	/* Monitor service call */

/*
 * Interrupt vector number for T-Kernel
 */
#define TRAP_SVC	0x71	/* System call, Extension SVC */
#define TRAP_RETINT	0x72	/* tk_ret_int() system call */
#define TRAP_DISPATCH	0x73	/* Task dispatcher call */
#define TRAP_DCT	0x74	/* Delayed context trap */
#define TRAP_LOADSR	0x75	/* SR register load function */
#define TRAP_DEBUG	0x76	/* Debugger support function */

/*
 * Interrupt vector number for Extension
 */
#define TRAP_KILLPROC	0x77	/* Force process termination request */

#endif /* __TK_SYSDEF_DEPEND_H__ */