asm_depend.h

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)asm_depend.h (tk/SH7727)
 *
 *	Assembler Macro for SH7727
 */

#ifndef __TK_ASM_DEPEND_H__
#define __TK_ASM_DEPEND_H__

/*
 * Stack state at Exception/Interrupt
 *
 *		+-------+
 *   new ISP ->	| R0	|
 *		| SPC	|
 *		| SSR	|
 *		| MDR	|
 *		| USP	| Save USP only when switching to the system stack
 *		+-------+
 *   old ISP ->
 *
 * Macro
 *	INT_ENTER	* EIT entry
 *			Save to the interrupt stack as shown above.
 *	INT_RETURN	* EIT return
 *			Restore from the interrupt stack shown above
 *			and return (RTE).
 *
 *	If it is not the task independent part like extension SVC,
 *	need to move to the system stack before dispatch is enabled
 *	(interrupt enable) becauaes the interrupt stack can not be
 *	used continuously.
 *
 *	MOVE_ISP_SSP	Move from the interrupt stack to the system stack
 *	MOVE_SSP_ISP	Move from the system stack to the interrupt stack
 */

/*
 * Exception/Interrupt entry common processing
 */
 .macro	INT_ENTER name

	mov	#3, r7		// If CPL > 0, switch to system stack
	tst	r7, MDR
	bt	l_nochg_\name

	mov.l	SP, @-ISP	// User stack save
	mov	SST, SP		// Switch to system stack

  l_nochg_\name:
	mov.l	MDR, @-ISP	// Operation mode save 
	shll16	MDR		// Operation mode update 

	stc.l	ssr, @-ISP	// SSR save
	stc.l	spc, @-ISP	// SPC save 
	mov.l	r0,  @-ISP	// R0 save

	stc	sr, r0		// Interrupt disable SR.I = 15
	or	#SR_I(15), r0
	ldc	r0, sr

 .endm

/*
 * Exception/Interrupt return common processing
 *	Execute by setting SR.BL=1 and SR.RB=1 
 */
 .macro	INT_RETURN name

  l_retry_\name:
	mov.l	@ISP+, r0	// R0 restore
	ldc.l	@ISP+, spc	// SPC restore
	ldc.l	@ISP+, ssr	// SSR restore
	mov.l	@ISP+, MDR	// MDR restore

	mov	#3, r7		// If PPL > 0, switch to user stack
	tst	r7, MDR
	bt	l_norst_\name

	cmp/pz	MDR		// Check DCT request
	bt	l_nodct_\name

	add	#-4*4, ISP	// Return stack
	shll16	MDR		// Return operation mode

	mov.l	BL_\name, r7
	stc	sr, r0
	xor	r0, r7
	ldc	r7, sr		// SR.BL=0
	trapa	#TRAP_DCT	// Delayed context trap
	ldc	r0, sr		// SR.BL=1
	bra	l_retry_\name
	nop

  l_nodct_\name:
	mov.l	@ISP+, SP	// Switch to user stack

  l_norst_\name:

	rte
	nop

		.balign	4
  BL_\name:	.long	SR_BL

 .endm

/*
 * TRAPA return common processing
 *	Execute by setting SR.BL=1 and SR.RB=1
 */
 .macro	CALL_RETURN name
	INT_RETURN \name
 .endm

/*
 * ISP -> SSP move
 *	Execute by setting SR.BL=0 and SR.RB=1
 */
 .macro	MOVE_ISP_SSP name

	mov.l	@(3*4,ISP), r0	// MDR
	tst	#3, r0		// Check whether USP is saved
	bt	l_nousp1_\name	// If PPL > 0, USP is saved

	mov.l	@(4*4,ISP), r0	// USP
	mov.l	r0, @-SP
  l_nousp1_\name:
	mov.l	@(3*4,ISP), r0	// MDR
	mov.l	r0, @-SP
	mov.l	@(2*4,ISP), r0	// SSR
	mov.l	r0, @-SP
	mov.l	@(1*4,ISP), r0	// SPC
	mov.l	r0, @-SP
	mov.l	@(0*4,ISP), r0	// R0
	mov.l	r0, @-SP

	bt	l_nousp2_\name	// Waste from interrupt stack
	add	#1*4, ISP
  l_nousp2_\name:
	add	#4*4, ISP

 .endm

/*
 * SSP -> ISP move
 *	Execute by setting SR.BL=0 and SR.RB=1
 */
 .macro	MOVE_SSP_ISP name

	mov.l	@(3*4,SP), r0	// MDR
	tst	#3, r0		// Check whether USP is saved
	bt	l_nousp3_\name	// If PPL > 0, USP is saved

	mov.l	@(4*4,SP), r0	// USP
	mov.l	r0, @-ISP
  l_nousp3_\name:
	mov.l	@(3*4,SP), r0	// MDR
	mov.l	r0, @-ISP
	mov.l	@(2*4,SP), r0	// SSR
	mov.l	r0, @-ISP
	mov.l	@(1*4,SP), r0	// SPC
	mov.l	r0, @-ISP
	mov.l	@(0*4,SP), r0	// R0
	mov.l	r0, @-ISP

	bt	l_nousp4_\name	// Waste from system stack
	add	#1*4, SP
  l_nousp4_\name:
	add	#4*4, SP

 .endm

/*
 * Task exception handler entry
 *
 *		+---------------+
 *  USP(R15) ->	| save SR	| Restore when returning from handler SR
 *	+4	| retadr	| Return address from handler
 *	+8	| texcd		| Exception code
 *		+---------------+
 *
 *	Note that the privilege instruction is not available
 *	because it may be executed by the user mode.
 */
 .macro TEXHDR_ENTRY texhdr

	mov.l	r4, @-r15		// R4 save
	mov.l	@(3*4, r15), r4		// R4 = texcd
	mov.l	r0, @(3*4, r15)		// R0 save

	stc.l	gbr,  @-r15		// Other register saves
	sts.l	pr,   @-r15
	sts.l	mach, @-r15
	sts.l	macl, @-r15
	mov.l	r1,   @-r15
	mov.l	r2,   @-r15
	mov.l	r3,   @-r15
	mov.l	r5,   @-r15
	mov.l	r6,   @-r15
	mov.l	r7,   @-r15

	mov.l	l_\texhdr, r0
	jsr	@r0			// call texhdr(texcd)
	nop

	mov.l	@r15+, r7		// Register restore
	mov.l	@r15+, r6
	mov.l	@r15+, r5
	mov.l	@r15+, r3
	mov.l	@r15+, r2
	mov.l	@r15+, r1
	lds.l	@r15+, macl
	lds.l	@r15+, mach
	lds.l	@r15+, pr
	ldc.l	@r15+, gbr
	mov.l	@r15+, r4

	mov.l	@r15+, r0		// Restore SR
	trapa	#TRAP_LOADSR		// R0 -> SR

	mov.l	@r15+, r0		// Return address from handler
	jmp	@r0
	mov.l	@r15+, r0		// R0 restore

		.balign	4
  l_\texhdr:	.long	Csym(\texhdr)	// Handler body address

 .endm

#endif /* __TK_ASM_DEPEND_H__ */