sysdef_depend.h

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)sysdef_depend.h (tk/MB87Q1100)
 *
 *	Definition about MB87Q1100
 *
 *	Included also from assembler program.
 */

#ifndef __TK_SYSDEF_DEPEND_H__
#define __TK_SYSDEF_DEPEND_H__

/*
 * Program status register (PSR)
 */
#define PSR_N		0x80000000	/* Condition flag Negative */
#define PSR_Z		0x40000000	/* Zero */
#define PSR_C		0x20000000	/* Carry */
#define PSR_V		0x10000000	/* Overflow */

#define PSR_Q		0x08000000	/* Sticky overflow */
#define PSR_J		0x01000000	/* Jazelle mode */

#define PSR_I		0x00000080	/* Interrupt (IRQ) disable */
#define PSR_F		0x00000040	/* Fast Interrupt (FIQ) disable */
#define PSR_T		0x00000020	/* Thumb mode */

#define PSR_DI		( PSR_I )	/* All Interrupts disable */

#define PSR_M(n)	( n )		/* Processor mode 0-31 */
#define PSR_USR		PSR_M(16)	/* User mode */
#define PSR_FIQ		PSR_M(17)	/* Fast Interrupt (FIQ) mode */
#define PSR_IRQ		PSR_M(18)	/* Interrupt (IRQ) mode */
#define PSR_SVC		PSR_M(19)	/* Supervisor mode */
#define PSR_ABT		PSR_M(23)	/* Abort mode */
#define PSR_UND		PSR_M(27)	/* Undefined order mode */
#define PSR_SYS		PSR_M(31)	/* System mode */

/*
 * Task mode flag
 *	System shared information 'taskmode' 
 */
#define TMF_CPL(n)	( (n) )		/* Current protection level(0-3) */
#define TMF_PPL(n)	( (n) << 16 )	/* Previous protection level(0-3) */

/*
 * System control coprocessor (CP15): Control register (CR1)
 */
#define CR1_M	0x0001	/* MMU enable */
#define CR1_A	0x0002	/* Alignment check enable */
#define CR1_C	0x0004	/* Cache enable */
#define CR1_W	0x0008	/* Write buffer enable */
#define CR1_B	0x0080	/* Endian (1=Big endian) */
#define CR1_S	0x0100	/* System protection */
#define CR1_R	0x0200	/* ROM protection */
#define CR1_I	0x1000	/* Instruction cache enable */
#define CR1_V	0x2000	/* High vector */
#define CR1_RR	0x4000	/* Round robin cache */
#define CR1_L4	0x8000	/* ARMv4 compatible mode */

#define CR1_nF	0x40000000	/* clock mode (Fast)  */
#define CR1_iA	0x80000000	/* clock mode (Async) */

/*
 * Fault status (CP15:CR5)
 */
#define FSR_Alignment	0x1	/* 00x1 : Miss-alignment access */
#define FSR_BusErrorT	0xc	/* 11x0 : Bus error when converting address */
#define FSR_Translation	0x5	/* 01x1 : No page when converting address */
#define FSR_Domain	0x9	/* 10x1 : Domain access violation */
#define FSR_Permission	0xd	/* 11x1 : Access violation */
#define FSR_BusErrorL	0x4	/* 01x0 : Bus error when fetching line */
#define FSR_BusErrorO	0x8	/* 10x0 : Other bus errors */
#define FSR_Section	0x0	/* xx0x : Section */
#define FSR_Page	0x2	/* xx1x : Page */
#define FSR_TypeMask	0xd	/* Type mask */

/* ------------------------------------------------------------------------ */

/*
 * Interrupt controller (IRC_A, EXIRC_A)
 *	Register size W
 */

#define IRCA(n)		( 0xfffffe00 + (n) )
#define AIRQF		IRCA(0x000)	/* IRQ flag */
#define AIRQM		IRCA(0x004)	/* IRQ mask */
#define AILM		IRCA(0x008)	/* Interrupt mask level */
#define AICRMN		IRCA(0x00c)	/* ICR monitor */
#define ASWIR0		IRCA(0x014)	/* Software interrupt 0 */
#define ASWIR1		IRCA(0x018)	/* Software interrupt 1 */
#define ATBR		IRCA(0x01c)	/* Table base */
#define AVCT		IRCA(0x020)	/* Interrupt vector */
#define AICR(n)		IRCA(0x030+(n)*4) /* Interrupt control (0-31) */

#define EXIRCA(i, n)	( 0xfffe4000 + (n) + (i)*0x800 )
#define AEIENB(i)	EXIRCA(i,0x00)	/* Interrupt enable */
#define AEIREQ(i)	EXIRCA(i,0x04)	/* Interrupt status / clear */
#define AEILVL(i)	EXIRCA(i,0x08)	/* Trigger mode */

/*
 * CPLD interrupt control register
 *	Register size B
 */
#define TINT_STS	0x11003000	/* Interrupt status */
#define TINT_MSK	0x11003002	/* Interrupt mask */

/*
 * FPGA interrupt control register
 *	Register size B
 */
#define IRQ_MASK1	0x11002028	/* Interrupt mask 1 */
#define IRQ_MASK2	0x1100202a	/* Interrupt mask 2 */
#define IRQ_STR1	0x1100202c	/* Interrupt status 1 */
#define IRQ_STR2	0x1100202e	/* Interrupt status 2 */

/* ------------------------------------------------------------------------ */
/*
 * Software interrupt number for T-Monitor
 */
#define SWI_MONITOR	4	/* T-Monitor service call */

/*
 * Software interrupt number for T-Kernel 
 */
#define SWI_SVC		6	/* T-Kernel system call/extension SVC */
#define SWI_RETINT	7	/* tk_ret_int() system call */
#define SWI_DISPATCH	8	/* Task dispatcher */
#define SWI_DEBUG	9	/* Debugger support function */

/*
 * Software interrupt number for Extension
 */
#define SWI_KILLPROC	11	/* Force process termination request */

/* ------------------------------------------------------------------------ */

/*
 * Location and size of task specific space
 *	Number of entries and index number of first level page table
 */
#define TOP_PDIR_ENTRIES	0x400	/* 0x40000000 */
#define NUM_PDIR_ENTRIES	0x100	/* 0x40000000 - 0x50000000 */

#endif /* __TK_SYSDEF_DEPEND_H__ */