sysdef_depend.h

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)sysdef_depend.h (tk/M32104)
 *
 *	Definition about M32104
 *
 *	Included also from assembler program.
 */

#ifndef __TK_SYSDEF_DEPEND_H__

/*
 * PSW register
 */
#define PSW_C	0x00000001	/* Condition bit */
#define PSW_IE	0x00000040	/* Interrupt enable */
#define PSW_SM	0x00000080	/* Stack mode */
#define PSW_BC	0x00000100	/* Back up C */
#define PSW_BIE	0x00004000	/* Back up IE */
#define PSW_BSM	0x00008000	/* Back up SM */

/*
 * Cache control register
 */
#define CC_INCR1	0xffffff80	/* Non instruction cache area 1 */
#define CC_INCR2	0xffffff84	/* Non instruction cache area 2 */
#define CC_DNCR1	0xffffffa0	/* Non data cache area 1 */
#define CC_DNCR2	0xffffffa4	/* Non data cache area 2 */
#define CC_DNCR3	0xffffffa8	/* Non data cache area 3 */
#define CC_MCCR		0xfffffffc	/* Cache control register */

#define CC_NCSZ_2MB	6		/* Non cache size specify */
#define CC_NCSZ_16MB	3
#define CC_NCSZ_32MB	2
#define CC_NCSZ_NONE	15		/* No non-cache area */

#define CC_DCB		0x0400		/* Data cache writeback */
#define CC_DIV		0x0200		/* Data cache disable */
#define CC_IIV		0x0100		/* Order cache disable */
#define CC_DCM		0x0002		/* Data cache enable */
#define CC_ICM		0x0001		/* Order cache enable */

/*
 * Int. Interrupt controller (ICU1)
 *	Register size W
 */
#define ICU1(n)		(0x007ff000 + (n))
#define ICU1_ISTS	(ICU1(0x004))		/* Interrupt status */
#define ICU1_IREQ(n)	(ICU1(0x008) + (n)*4)	/* Interrupt request 0,1 */
#define ICU1_SBICR	(ICU1(0x018))		/* System break interrupt control */
#define ICU1_IMASK	(ICU1(0x01c))		/* Interrupt mask */
#define ICU1_CR(n)	(ICU1(0x1fc) + (n)*4)	/* Interrupt control 1-63 */

/*
 * PLD interrupt controller (ICU2)
 *	Register size H
 */
#define ICU2(n)		(0x02c08000 + (n))
#define ICU2_ISTS	(ICU2(0x002))		/* Interrupt status */
#define ICU2_IREQ(n)	(ICU2(0x004) + (n)*2)	/* Interrupt request 0 */
#define ICU2_CR(n)	(ICU2(0x0fe) + (n)*2)	/* Interrupt control 1-31 */

/* Interrupt control register */
#define ICUCR_IEN	0x1000	/* Interrupt request accept enable */
#define ICUCR_IREQ	0x0100	/* Interrupt request status / Interrupt clear */
#define ICUCR_ISMOD	0x0070	/* Interrupt sense mode */
#define ICUCR_ILEVEL	0x0007	/* Interrupt priority level */

/*
 * Trap number for T-Kernel
 */
#define TRAP_SVC	2	/* T-Kernel system call/extended SVC */
#define TRAP_RETINT	3	/* tk_ret_int() system call */
#define TRAP_DISPATCH	4	/* Task dispatcher */
#define TRAP_DEBUG	5	/* Debugger support function */

/*
 * Trap number for T-Monitor
 */
#define TRAP_MONITOR	0	/* T-Monitor service call */
#define TRAP_BREAK	1	/* Break point */

/*
 * Interrupt vector number for Extension
 */
#define TRAP_KILLPROC	6	/* Force process termination request */

#endif /* __TK_SYSDEF_DEPEND_H__ */