int.c

使用广泛的日本著名的开源嵌入式实时操作系统T-Kernel的源码

/*
 *----------------------------------------------------------------------
 *    T-Kernel
 *
 *    Copyright (C) 2004-2006 by Ken Sakamura. All rights reserved.
 *    T-Kernel is distributed under the T-License.
 *----------------------------------------------------------------------
 *
 *    Version:   1.02.02
 *    Released by T-Engine Forum(http://www.t-engine.org) at 2006/8/9.
 *
 *----------------------------------------------------------------------
 */

/*
 *	@(#)int.c (libtk/M32104)
 *
 *	Interrupt controller 
 *
 *	Only values in the range 20(IV_INT0) - 115 can be
 *	specified in intvec.
 *	Proper operation cannot be guaranteed if values outside
 *	this range are specified.
 */

#include <basic.h>
#include <tk/syslib.h>
#include <sys/sysinfo.h>
#include <tk/sysdef.h>

/*
 * Disable interrupt/enable interrupt (restore)
 */
Inline UW DisInt( void )
{
	UW	psw;

	Asm("mvfc %0, psw" : "=r"(psw));
	Asm("mvtc %0, psw" :: "r"(psw & ~PSW_IE));

	return psw;
}
Inline void EnaInt( UW psw )
{
	Asm("mvtc %0, psw" :: "r"(psw));
}

/*
 * Set interrupt mode
 *	Sets the interrupt specified in intvec to the mode
 *	specified in mode.
 *	The mode types that can be specified depend on the
 *	type of interrupt(intvec).
 *	The mode value is set in the interrupt register as is
 *	without modification.
 */
EXPORT void SetIntMode( INTVEC intvec, UINT mode )
{
	W	n;

	if ( intvec < (INTVEC)EIT_ICU2(0) ) {
		/* ICU1: built-in interrupt controller */
		n = (INT)intvec - EIT_ICU1(0);
		out_w(ICU1_CR(n), mode);
	} else {
		/* ICU2: PLD interrupt controller */
		n = (INT)intvec - EIT_ICU2(0);
		out_h(ICU2_CR(n), mode);
	}
}

/*
 * Enable interrupt 
 *	Enables the interrupt specified in intvec at the level
 *	priority. The level value is in the range 0 - 7
 *	(7 is effectively interrupt disabled). 
 *	The following interrupt control register bits are set.
 *	IEN = 1 (enable interrupt request accept)
 *	ILEVEL = level
 *	All other bits remain unchanged.
*/
EXPORT void EnableInt( INTVEC intvec, INT level )
{
	UW	psw, icucr;
	W	n;

	psw = DisInt();
	if ( intvec < (INTVEC)EIT_ICU2(0) ) {
		/* ICU1: built-in interrupt controller */
		n = (INT)intvec - EIT_ICU1(0);
		icucr = in_w(ICU1_CR(n)) & ~ICUCR_ILEVEL;
		out_w(ICU1_CR(n), icucr | level | ICUCR_IEN);
	} else {
		/* ICU2: PLD interrupt controller */
		n = (INT)intvec - EIT_ICU2(0);
		icucr = in_h(ICU2_CR(n)) & ~ICUCR_ILEVEL;
		out_h(ICU2_CR(n), icucr | level | ICUCR_IEN);
	}
	EnaInt(psw);
}

/*
 * Disable interrupt 
 *	Disables the interrupt specified in intvec.
 *	The following interrupt control register bit is set.
 *	ILEVEL = 7
 *	All other bits remain unchanged (IEN does not change).
 */
EXPORT void DisableInt( INTVEC intvec )
{
	UW	psw, icucr;
	W	n;

	psw = DisInt();
	if ( intvec < (INTVEC)EIT_ICU2(0) ) {
		/* ICU1: built-in interrupt controller */
		n = (INT)intvec - EIT_ICU1(0);
		icucr = in_w(ICU1_CR(n));
		out_w(ICU1_CR(n), icucr | ICUCR_ILEVEL);
	} else {
		/* ICU2: PLD interrupt controller */
		n = (INT)intvec - EIT_ICU2(0);
		icucr = in_h(ICU2_CR(n));
		out_h(ICU2_CR(n), icucr | ICUCR_ILEVEL);
	}
	EnaInt(psw);
}

/*
 * Clear interrupt request 
 *	Clears the intvec interrupt request.
 *	The following interrupt control register bit is set.
 *	IREQ = 1
 *	All other bits remain unchanged.
 */
EXPORT void ClearInt( INTVEC intvec )
{
	UW	psw, icucr;
	W	n;

	psw = DisInt();
	if ( intvec < (INTVEC)EIT_ICU2(0) ) {
		/* ICU1: built-in interrupt  controller */
		n = (INT)intvec - EIT_ICU1(0);
		icucr = in_w(ICU1_CR(n));
		out_w(ICU1_CR(n), icucr | ICUCR_IREQ);
	} else {
		/* ICU2: PLD interrupt controller */
		n = (INT)intvec - EIT_ICU2(0);
		icucr = in_h(ICU2_CR(n));
		out_h(ICU2_CR(n), icucr | ICUCR_IREQ);
	}
	EnaInt(psw);
}

/*
 * Checks for interrupt requests 
 *	Reads the interrupt request register and checks for
 *	intvec interrupt requests.
 *	If an interrupt request is found, returns TRUE (other than 0).
 */
EXPORT BOOL CheckInt( INTVEC intvec )
{
	UW	req;
	W	n;

	if ( intvec < (INTVEC)EIT_ICU2(0) ) {
		/* ICU1: built-in interrupt controller */
		if ( intvec < (INTVEC)EIT_ICU1(32) ) {
			req = in_w(ICU1_IREQ(0));
			n = (INT)intvec - EIT_ICU1(0);
		} else {
			req = in_w(ICU1_IREQ(1));
			n = (INT)intvec - EIT_ICU1(32);
		}
		return (BOOL)((req >> (31 - n)) & 0x00000001U);
	} else {
		/* ICU2: PLD interrupt controller */
		if ( intvec < (INTVEC)EIT_ICU2(16) ) {
			req = in_h(ICU2_IREQ(0));
			n = (INT)intvec - EIT_ICU2(0);
		} else {
			req = in_h(ICU2_IREQ(1));
			n = (INT)intvec - EIT_ICU2(16);
		}
		return (BOOL)((req >> (15 - n)) & 0x00000001U);
	}
}