initsystem.c

ccs3.1 omap5910 platform

/***************************************************
公司:      好易通科技有限公司
产品名:    TETRA数字集群终端
CPU:       OMAP5910
功能:      初始化系统
作者:      袁林
编写时间:  2005.01.12
修改时间： 2005.06.06
****************************************************/
#include "InitSystem.h"
#include "type.h"

void InitSystem( void )
{
	UINT16 i;
	
	*((unsigned long *)0xfffecb00) = 0;/* mpu_l1_itr,interrupt register,clear interrupt request*/
	*((unsigned long *)0xfffecb04) = 0xffffffff;/* mpu_l1_mir,mask interrupt reg,masker all interrupt request */
	*((unsigned long *)0xfffe0000) = 0;/* mpu_l2_itr,interrupt register */
	*((unsigned long *)0xfffe0004) = 0xffffffff;/* mpu_l2_mir,mask interrupt reg */
	
	/* select native mode */
	*(volatile unsigned long *)0xFFFE100C = 0x0000eaef;  //使能重新配置1510
	 
	// Set clocking scheme to synchronous scalable: 010,CLOCK_SELECT(13-11)
	i = pMPU_CRPC->arm_sysst;
	i |= 0x1000; //0xfffece18   将一个数的某些位置 1，其余不变
	i &= 0xd7ff; //0xfffece18   将一个数的某些位置 0，其余保留
	pMPU_CRPC->arm_sysst = i;
	
	/* ARM_CKCTL:DSPMMU_CLK = GEN2/2,TC_CLK = GEN3/2,DSP_CLK = GEN2,ARM_CLK = GEN1 */
	/* LCD_CLK = GEN3/4, PER_CLK = GEN1/4 ,Use CLKIN for TIMX0 ,enable dsp clock */
	i = 0;
	i = MPUCLOCKREGVAL;        //0x250a;
	pMPU_CRPC->arm_ckctl = i;
	
	// enable dsp by setting DSP_RST and DSP_EN fields of ARM_RSTCT1
	i = 0;
	i = pMPU_CRPC->arm_rstct1;
	i |= 0x6;
	pMPU_CRPC->arm_rstct1 = i;
	
	//CLKRST_reset(CLKRSTVAL);  /* reset arm and internal peripheral power on,may no required */
	//PLL_setfrequence();  /* set dpll1 frequence */
	/* mult = 20,clkout = clkref/2 = 6 MHz,enable dpll lock mode,so dpll = 20*6 = 120MHz,IOB = BREAKIN = 1 */
	*(volatile unsigned short *)0xFFFECF00 = 0x2a30;  //0x2a33
	//SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_MULT_POS,DPLL_DPLL1_CTL_REG_PLL_MULT_NUMB,20);
	//SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_DIV_POS,DPLL_DPLL1_CTL_REG_PLL_DIV_NUMB,2);
	//SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_IOB_POS,DPLL_DPLL1_CTL_REG_IOB_NUMB,DPLL_DPLL1_CTL_REG_IOB_RES_VAL);
	//SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_BREAKLN_POS,DPLL_DPLL1_CTL_REG_BREAKLN_NUMB,True);
	//SetGroupBits16(DPLL_DPLL1_CTL_REG,DPLL_DPLL1_CTL_REG_PLL_ENABLE_POS,DPLL_DPLL1_CTL_REG_PLL_ENABLE_NUMB,ENABLE);
	
	/* Wait DPLL to lock ,equal 1 indicates dpll enter lock mode *///
	while( !GetGroupBits(DPLL_DPLL1_CTL_REG, DPLL_DPLL1_CTL_REG_LOCK_POS,	DPLL_DPLL1_CTL_REG_LOCK_NUMB));
	
	/* set ARM clock and enable DSP */
	/* enable clocks for devices listed ARM_IDLECT2 0xfffece10 */
	i = 0;
	i = pMPU_CRPC->arm_idlect2;
	i |= 0x03df ;  // gpiock,dmackreq,timck,apick,lbck,lcdck,perck,xorpck,wdtck
	pMPU_CRPC->arm_idlect2 = i;
	
	// enable all ARM peripherals
	CLKRST_TogglePeripheralResetPin(HIGH_LEVEL); /* mpuper_nrst inactive */
	
	/* set dsp side clock domain and enable dsp peripherals */
	// TIMX0 = GPIOX0 = CLKIN,GPIODIV = 0
	i = 0;
	i = pDSP_CRPC->dsp_ckctl;
	i &= 0x0;
	pDSP_CRPC->dsp_ckctl = i;
	
	/* enable clocks for devices listed DSP_IDLECT2 0x4000 */
	i = 0;
	i = pDSP_CRPC->dsp_idlect2;
	i |= 0x0033 ;  // timck,gpiock,xorpck,wdtck
	pDSP_CRPC->dsp_idlect2 = i;
	
	// enable all DSP peripherals
	i = 0;
	i = pDSP_CRPC->dsp_rstct2;
	i |= 0x1;                 /* dspper_nrst inactive */
	pDSP_CRPC->dsp_rstct2 = i;

}


UINT16 SetGroupBits16(UINT16 registre,BYTE position,BYTE width,BYTE value)
{
   registre&=~((0xFFFF>>(16-(width)))<<(position));
   registre|=((value&(0xFFFF>>(16-(width))))<<(position));
   return(registre);
}

void CLKRST_TogglePeripheralResetPin(BOOL State)
{
/*    SetGroupBits(CLKRST_ARM_RSTCT2,CLKRST_ARM_RSTCT2_PER_EN_POS,CLKRST_ARM_RSTCT2_PER_EN_NUMB,State);*/
    UWORD16 temp;

	temp = CLKRST_ARM_RSTCT2; /* 0xfffece14 */
	temp = SetGroupBits16(temp,CLKRST_ARM_RSTCT2_PER_EN_POS,CLKRST_ARM_RSTCT2_PER_EN_NUMB,State);
	CLKRST_ARM_RSTCT2 = temp;
}

void    CLKRST_reset(BYTE Rstval)  /* reset arm and internal peripheral power on,may no required  */
{
    //enable arm and internal peripheral reset,SW_RST bit
    pMPU_CRPC->arm_rstct1 |= Rstval;
}