initsystem.h

ccs3.1 omap5910 platform

#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_POS        3
#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_NUMB       1
#define CLKRST_ARM_IDLECT1_IDLLCD_ARM_RES_VAL    0x0
//R/W

#define CLKRST_ARM_IDLECT1_IDLPER_ARM_POS        2
#define CLKRST_ARM_IDLECT1_IDLPER_ARM_NUMB       1
#define CLKRST_ARM_IDLECT1_IDLPER_ARM_RES_VAL    0x0
//R/W

#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_POS       1
#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_NUMB      1
#define CLKRST_ARM_IDLECT1_IDLXORP_ARM_RES_VAL   0x0
//R/W

#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_POS        0
#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_NUMB       1
#define CLKRST_ARM_IDLECT1_IDLWDT_ARM_RES_VAL    0x0
//R/W


//CLKRST_ARM_IDLECT2
//-------------------                            // 0xFFFECE08
#define CLKRST_ARM_IDLECT2                       GetIo16(CLKRST_BASE_ADDR+0x08)


#define CLKRST_ARM_IDLECT2_EN_LBFREECK_POS       10
#define CLKRST_ARM_IDLECT2_EN_LBFREECK_NUMB      1
#define CLKRST_ARM_IDLECT2_EN_LBFREECK_RES_VAL   0x0
//R/W

#define CLKRST_ARM_IDLECT2_EN_GPIOCK_POS         9
#define CLKRST_ARM_IDLECT2_EN_GPIOCK_NUMB        1
#define CLKRST_ARM_IDLECT2_EN_GPIOCK_RES_VAL     0x0
//R/W

#define CLKRST_ARM_IDLECT2_DMACK_REQ_POS         8
#define CLKRST_ARM_IDLECT2_DMACK_REQ_NUMB        1
#define CLKRST_ARM_IDLECT2_DMACK_REQ_RES_VAL     0x1
//R/W

#define CLKRST_ARM_IDLECT2_EN_TIMCK_POS          7
#define CLKRST_ARM_IDLECT2_EN_TIMCK_NUMB         1
#define CLKRST_ARM_IDLECT2_EN_TIMCK_RES_VAL      0X0
//R/W

#define CLKRST_ARM_IDLECT2_EN_APICK_POS          6
#define CLKRST_ARM_IDLECT2_EN_APICK_NUMB         1
#define CLKRST_ARM_IDLECT2_EN_APICK_RES_VAL      0x0
//R/W

#define CLKRST_ARM_IDLECT2_EN_HSABCK_POS         5
#define CLKRST_ARM_IDLECT2_EN_HSABCK_NUMB        1
#define CLKRST_ARM_IDLECT2_EN_HSABCK_RES_VAL     0X0
//R/W

#define CLKRST_ARM_IDLECT2_EN_LBCK_POS           4
#define CLKRST_ARM_IDLECT2_EN_LBCK_NUMB          1
#define CLKRST_ARM_IDLECT2_EN_LBCK_RES_VAL       0X0
//R/W

#define CLKRST_ARM_IDLECT2_EN_LCDCK_POS          3
#define CLKRST_ARM_IDLECT2_EN_LCDCK_NUMB         1
#define CLKRST_ARM_IDLECT2_EN_LCDCK_RES_VAL      0x0
//R/W

#define CLKRST_ARM_IDLECT2_EN_PERCK_POS          2
#define CLKRST_ARM_IDLECT2_EN_PERCK_NUMB         1
#define CLKRST_ARM_IDLECT2_EN_PERCK_RES_VAL      0x0
//R/W

#define CLKRST_ARM_IDLECT2_EN_XORPCK_POS         1
#define CLKRST_ARM_IDLECT2_EN_XORPCK_NUMB        1
#define CLKRST_ARM_IDLECT2_EN_XORPCK_RES_VAL     0x0
//R/W

#define CLKRST_ARM_IDLECT2_EN_WDTCK_POS          0
#define CLKRST_ARM_IDLECT2_EN_WDTCK_NUMB         1
#define CLKRST_ARM_IDLECT2_EN_WDTCK_RES_VAL      0x0
//R/W


//CLKRST_ARM_EWUPCT
//-------------------                            // 0xFFFECE0C
#define CLKRST_ARM_EWUPCT                        GetIo16(CLKRST_BASE_ADDR+0x0C)


#define CLKRST_ARM_EWUPCT_REPWR_EN_POS           5
#define CLKRST_ARM_EWUPCT_REPWR_EN_NUMB          1
#define CLKRST_ARM_EWUPCT_REPWR_EN_RES_VAL       0x1
//R/W

#define CLKRST_ARM_EWUPCT_EXTPW_POS              0
#define CLKRST_ARM_EWUPCT_EXTPW_NUMB             5
#define CLKRST_ARM_EWUPCT_EXTPW_RES_VAL          0xF
//R/W


//CLKRST_ARM_RSTCT1
//-------------------                            // 0xFFFECE10
#define CLKRST_ARM_RSTCT1                        GetIo16(CLKRST_BASE_ADDR+0x10)


#define CLKRST_ARM_RSTCT1_SW_RST_POS             3
#define CLKRST_ARM_RSTCT1_SW_RST_NUMB            1
#define CLKRST_ARM_RSTCT1_SW_RST_RES_VAL         0x0
//R/W

#define CLKRST_ARM_RSTCT1_DSP_RST_POS            2
#define CLKRST_ARM_RSTCT1_DSP_RST_NUMB           1
#define CLKRST_ARM_RSTCT1_DSP_RST_RES_VAL        0x0
//R/W

#define CLKRST_ARM_RSTCT1_DSP_EN_POS             1
#define CLKRST_ARM_RSTCT1_DSP_EN_NUMB            1
#define CLKRST_ARM_RSTCT1_DSP_EN_RES_VAL         0x0
//R/W

#define CLKRST_ARM_RSTCT1_ARM_RST_POS            0
#define CLKRST_ARM_RSTCT1_ARM_RST_NUMB           1
#define CLKRST_ARM_RSTCT1_ARM_RST_RES_VAL        0x0
//R/W


//CLKRST_ARM_RSTCT2
//-------------------                            // 0xFFFECE14
#define CLKRST_ARM_RSTCT2                        GetIo16(CLKRST_BASE_ADDR+0x14)


#define CLKRST_ARM_RSTCT2_PER_EN_POS             0
#define CLKRST_ARM_RSTCT2_PER_EN_NUMB            1
#define CLKRST_ARM_RSTCT2_PER_EN_RES_VAL         0x0
//R/W


//CLKRST_ARM_SYSST
//-------------------                            // 0xFFFECE18
#define CLKRST_ARM_SYSST                         GetIo16(CLKRST_BASE_ADDR+0x18)


#define CLKRST_ARM_SYSST_CLOCK_SELECT_POS        11
#define CLKRST_ARM_SYSST_CLOCK_SELECT_NUMB       3
#define CLKRST_ARM_SYSST_CLOCK_SELECT_RES_VAL    0x0
//R/W

#define CLKRST_ARM_SYSST_IDLE_DSP_POS            6
#define CLKRST_ARM_SYSST_IDLE_DSP_NUMB           1
#define CLKRST_ARM_SYSST_IDLE_DSP_RES_VAL        0x0
//R

#define CLKRST_ARM_SYSST_POR_POS                 5
#define CLKRST_ARM_SYSST_POR_NUMB                1
#define CLKRST_ARM_SYSST_POR_RES_VAL             0X0
//R/C

#define CLKRST_ARM_SYSST_EXT_RST_POS             4
#define CLKRST_ARM_SYSST_EXT_RST_NUMB            1
#define CLKRST_ARM_SYSST_EXT_RST_RES_VAL         0x0
//R/C

#define CLKRST_ARM_SYSST_ARM_MCRST_POS           3
#define CLKRST_ARM_SYSST_ARM_MCRST_NUMB          1
#define CLKRST_ARM_SYSST_ARM_MCRST_RES_VAL       0x0
//R/C

#define CLKRST_ARM_SYSST_ARM_WDRST_POS           2
#define CLKRST_ARM_SYSST_ARM_WDRST_NUMB          1
#define CLKRST_ARM_SYSST_ARM_WDRST_RES_VAL       0x0
//R/C

#define CLKRST_ARM_SYSST_GLOB_SWRST_POS          1
#define CLKRST_ARM_SYSST_GLOB_SWRST_NUMB         1
#define CLKRST_ARM_SYSST_GLOB_SWRST_RES_VAL      0x0
//R/C

#define CLKRST_ARM_SYSST_DSP_WDRST_POS           0
#define CLKRST_ARM_SYSST_DSP_WDRST_NUMB          1
#define CLKRST_ARM_SYSST_DSP_WDRST_RES_VAL       0x0
//R/C


//CLKRST_ARM_CKOUT1
//-------------------                            // 0xFFFECE1C
#define CLKRST_ARM_CKOUT1                        GetIo16(CLKRST_BASE_ADDR+0x1C)


#define CLKRST_ARM_CKOUT1_TCLKOUT_POS            4
#define CLKRST_ARM_CKOUT1_TCLKOUT_NUMB           2
#define CLKRST_ARM_CKOUT1_TCLKOUT_RES_VAL        0x1
//R/W

#define CLKRST_ARM_CKOUT1_DCLKOUT_POS            2
#define CLKRST_ARM_CKOUT1_DCLKOUT_NUMB           2
#define CLKRST_ARM_CKOUT1_DCLKOUT_RES_VAL        0x1
//R/W

#define CLKRST_ARM_CKOUT1_ACLKOUT_POS            0
#define CLKRST_ARM_CKOUT1_ACLKOUT_NUMB           2
#define CLKRST_ARM_CKOUT1_ACLKOUT_RES_VAL        0x1
//R/W

//LOCAL BUS REGISTER
//LB_MPU_TIMEOUT
//-------------------                            // 0xFFFEC100
#define LOCAL_BUS_ARM_TIMEOUT                    GetIo16(MEM_ARM_LOCALBUS_ADDR+0x00)
#define LOCAL_BUS_ARM_HOLD_TIMER                 GetIo16(MEM_ARM_LOCALBUS_ADDR+0x04)

//CLKRST_ARM_CKOUT2
//-------------------                         // 0xFFFECE20
#define CLKRST_ARM_CKOUT2                     GetIo16(CLKRST_BASE_ADDR+0x20)
//R/W

struct MPU_CLK_reset_power_CTL
{
	volatile unsigned short arm_ckctl;
	volatile unsigned short reserved0;
	volatile unsigned short arm_idlect1;
	volatile unsigned short reserved1;
	volatile unsigned short arm_idlect2;//08
	volatile unsigned short reserved2;
	volatile unsigned short arm_ewupct;
	volatile unsigned short reserved3;
	volatile unsigned short arm_rstct1;//10
	volatile unsigned short reserved4;
	volatile unsigned short arm_rstct2;
	volatile unsigned short reserved5;
	volatile unsigned short arm_sysst;//18
	volatile unsigned short reserved6;
	volatile unsigned short reserved7;
	volatile unsigned short reserved8;
	volatile unsigned short reserved9;
	volatile unsigned short reserved10;
};
// arm clock,reset,power mode control register.
struct MPU_CLK_reset_power_CTL *pMPU_CRPC\
    =(struct MPU_CLK_reset_power_CTL *)MEM_ARM_CLKM_ADDR; //0xfffece00

struct Config_register_set
{
	volatile unsigned int FUNC_MUX_CTRL_0;//00
	volatile unsigned int FUNC_MUX_CTRL_1;//04
	volatile unsigned int FUNC_MUX_CTRL_2;//08
	volatile unsigned int COMP_MODE_CTRL_0;//0c
	volatile unsigned int FUNC_MUX_CTRL_3;//10
	volatile unsigned int FUNC_MUX_CTRL_4;//14
	volatile unsigned int FUNC_MUX_CTRL_5;//18
	volatile unsigned int FUNC_MUX_CTRL_6;//1c
	volatile unsigned int FUNC_MUX_CTRL_7;//20
	volatile unsigned int FUNC_MUX_CTRL_8;//24
	volatile unsigned int FUNC_MUX_CTRL_9;//28
	volatile unsigned int FUNC_MUX_CTRL_A;//2c
	volatile unsigned int FUNC_MUX_CTRL_B;//30
	volatile unsigned int FUNC_MUX_CTRL_C;//34
	volatile unsigned int FUNC_MUX_CTRL_D;//38
	volatile unsigned int reserved0;      //3c
	volatile unsigned int PULL_DWN_CTRL_0;//40
	volatile unsigned int PULL_DWN_CTRL_1;//44
	volatile unsigned int PULL_DWN_CTRL_2;//48
	volatile unsigned int PULL_DWN_CTRL_3;//4c
	volatile unsigned int GATE_INH_CTRL_0;//50
	volatile unsigned int reserved1;      //54
	volatile unsigned int reserved2;      //58
	volatile unsigned int reserved3;      //5c
	volatile unsigned int VOLTAGE_CTRL_0; //60
	volatile unsigned int reserved4;      //64
	volatile unsigned int reserved5;      //68
	volatile unsigned int reserved6;      //6c
	volatile unsigned int TEST_DBG_CTRL_0;//70
	volatile unsigned int reserved7;      //74
	volatile unsigned int reserved8;      //78
	volatile unsigned int reserved9;      //7c
	volatile unsigned int MOD_CONF_CTRL_0;//80
};
// configure register address
struct Config_register_set *pMPU_Config\
         = (struct Config_register_set *)CONFIGURATION_BASE_ADDRESS;//0xfffe1000

/* The two TI peripheral bridges interface. */
struct MPU_TIPB_struct
{
	volatile unsigned short TIPB_CNTL;
	volatile unsigned short reserved0;
	volatile unsigned short TIPBBUS_ALLOC;
	volatile unsigned short reserved1;
	volatile unsigned short MPU_TIPB_CNTL;
	volatile unsigned short reserved2;
	volatile unsigned short ENHANCED_TIPB_CNTL;
	volatile unsigned short reserved3;
	volatile unsigned short ADDRESS_DBG; /* Readonly. */
	volatile unsigned short reserved4;
	volatile unsigned short DATA_DEBUG_LOW; /* Readonly. */
	volatile unsigned short reserved5;
	volatile unsigned short DATA_DEBUG_HIGH; /* Readonly. */
	volatile unsigned short reserved6;
	volatile unsigned char DEBUG_CNTR_SIG; /* Readonly. */
};
   /* MPU private TIPB bridge control register address 0xfffeca00 */
   struct MPU_TIPB_struct *pMPU_TIPB1 = (struct MPU_TIPB_struct*)MEM_ARM_RHEA_PRIV__ADDR;
   /* MPU public TIPB bridge control register address 0xfffed300 */
   struct MPU_TIPB_struct *pMPU_TIPB2 = (struct MPU_TIPB_struct*)MEM_ARM_RHEA_PUB_ADDR;

struct DSP_CLK_reset_power_CTL
{
	volatile unsigned short dsp_ckctl;   //00
	volatile unsigned short reserved0;
	volatile unsigned short dsp_idlect1; //04
	volatile unsigned short reserved1;
	volatile unsigned short dsp_idlect2; //08
	volatile unsigned short reserved2;
	volatile unsigned short reserved3; //0c
	volatile unsigned short reserved4;
	volatile unsigned short reserved5; //10
	volatile unsigned short reserved6; //12
	volatile unsigned short dsp_rstct2;  //14
	volatile unsigned short reserved7;
	volatile unsigned short arm_sysst;   //18
	volatile unsigned short reserved8;
};
// arm clock,reset,power mode control register.
struct DSP_CLK_reset_power_CTL *pDSP_CRPC\
    =(struct DSP_CLK_reset_power_CTL *)0xE1008000;

UINT16 * WATCHDOGMODE = (UINT16 *) 0xFFFEC808;

#define TIMEOUT_LOCK    31000
#define MULTNUM         20
#define CLKRSTVAL       0x0008  /* reset arm and internal peripheral power on ,reset value */

#define MPUCLOCKREGVAL  0x250a  //3506
#define WATCHDOGSEQ1    0xF5
#define WATCHDOGSEQ2    0xA0


typedef enum { DPLL1, DPLL2, DPLL3 } DPLLTYPE_t;

#define GetGroupBits(registre,position,number)          ((registre & ((0xFFFFFFFF>>(32-number))<<position))>>position)
#define SetGroupBits(registre,position,number,value)    registre&=~((0xFFFFFFFF>>(32-number))<<position);\
                                                        registre|=(value<<position)
#define GetGroupBits16(registre,position,number)        (((registre) & ((0xFFFF>>(16-(number)))<<(position)))>>(position))
//#define SetGroupBits16(registre,position,width,value)   registre&=~((0xFFFF>>(16-(width)))<<(position));\
//                                                        registre|=((value&(0xFFFF>>(16-(width))))<<(position))

BOOL    CLKRST_DpllSetClockandLock( UWORD8 multiplier , UWORD8 divider, DPLLTYPE_t  dpllreglabel);
UINT16  SetGroupBits16(UINT16 registre,BYTE position,BYTE width,BYTE value);
void    CLKRST_TogglePeripheralResetPin(BOOL State);
void    CLKRST_reset(BYTE Rstval);  /* reset arm and internal peripheral power on,may no required  */

#endif