📄 dds.rpt
字号:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\mydds\dds.rpt
dds
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 3/ 96( 3%) 5/ 48( 10%) 2/ 48( 4%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\mydds\dds.rpt
dds
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 CLK
Device-Specific Information: e:\mydds\dds.rpt
dds
** EQUATIONS **
CLK : INPUT;
START : INPUT;
X : INPUT;
-- Node name is 'ADDRESS0'
-- Equation name is 'ADDRESS0', type is output
ADDRESS0 = REGIS6;
-- Node name is 'ADDRESS1'
-- Equation name is 'ADDRESS1', type is output
ADDRESS1 = REGIS7;
-- Node name is 'ADDRESS2'
-- Equation name is 'ADDRESS2', type is output
ADDRESS2 = REGIS8;
-- Node name is 'ADDRESS3'
-- Equation name is 'ADDRESS3', type is output
ADDRESS3 = REGIS9;
-- Node name is 'ADDRESS4'
-- Equation name is 'ADDRESS4', type is output
ADDRESS4 = REGIS10;
-- Node name is 'ADDRESS5'
-- Equation name is 'ADDRESS5', type is output
ADDRESS5 = REGIS11;
-- Node name is 'ADDRESS6'
-- Equation name is 'ADDRESS6', type is output
ADDRESS6 = REGIS12;
-- Node name is 'ADDRESS7'
-- Equation name is 'ADDRESS7', type is output
ADDRESS7 = REGIS13;
-- Node name is ':19' = 'REGIS6'
-- Equation name is 'REGIS6', location is LC1_B11, type is buried.
REGIS6 = DFFE( _EQ001, GLOBAL( CLK), VCC, VCC, VCC);
_EQ001 = REGIS6 & START & !X
# !REGIS6 & START & X;
-- Node name is ':18' = 'REGIS7'
-- Equation name is 'REGIS7', location is LC5_B13, type is buried.
REGIS7 = DFFE( _EQ002, GLOBAL( CLK), VCC, VCC, VCC);
_EQ002 = !REGIS6 & REGIS7 & START
# REGIS6 & !REGIS7 & START & X
# REGIS7 & START & !X;
-- Node name is ':17' = 'REGIS8'
-- Equation name is 'REGIS8', location is LC1_B13, type is buried.
REGIS8 = DFFE( _EQ003, GLOBAL( CLK), VCC, VCC, VCC);
_EQ003 = !_LC2_B13 & REGIS8 & START
# _LC2_B13 & !REGIS8 & START & X
# REGIS8 & START & !X;
-- Node name is ':16' = 'REGIS9'
-- Equation name is 'REGIS9', location is LC7_B13, type is buried.
REGIS9 = DFFE( _EQ004, GLOBAL( CLK), VCC, VCC, VCC);
_EQ004 = !_LC4_B13 & REGIS9 & START
# _LC4_B13 & !REGIS9 & START & X
# REGIS9 & START & !X;
-- Node name is ':15' = 'REGIS10'
-- Equation name is 'REGIS10', location is LC6_B11, type is buried.
REGIS10 = DFFE( _EQ005, GLOBAL( CLK), VCC, VCC, VCC);
_EQ005 = !_LC3_B13 & REGIS10 & START
# _LC3_B13 & !REGIS10 & START & X
# REGIS10 & START & !X;
-- Node name is ':14' = 'REGIS11'
-- Equation name is 'REGIS11', location is LC4_B11, type is buried.
REGIS11 = DFFE( _EQ006, GLOBAL( CLK), VCC, VCC, VCC);
_EQ006 = !_LC3_B11 & REGIS11 & START
# _LC3_B11 & !REGIS11 & START & X
# REGIS11 & START & !X;
-- Node name is ':13' = 'REGIS12'
-- Equation name is 'REGIS12', location is LC2_B11, type is buried.
REGIS12 = DFFE( _EQ007, GLOBAL( CLK), VCC, VCC, VCC);
_EQ007 = !_LC5_B11 & REGIS12 & START
# _LC5_B11 & !REGIS12 & START & X
# REGIS12 & START & !X;
-- Node name is ':12' = 'REGIS13'
-- Equation name is 'REGIS13', location is LC8_B11, type is buried.
REGIS13 = DFFE( _EQ008, GLOBAL( CLK), VCC, VCC, VCC);
_EQ008 = !_LC7_B11 & REGIS13 & START
# _LC7_B11 & !REGIS13 & START & X
# REGIS13 & START & !X;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B13', type is buried
_LC2_B13 = LCELL( _EQ009);
_EQ009 = REGIS6 & REGIS7;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:123' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B13', type is buried
_LC4_B13 = LCELL( _EQ010);
_EQ010 = REGIS6 & REGIS7 & REGIS8;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = LCELL( _EQ011);
_EQ011 = REGIS6 & REGIS7 & REGIS8 & REGIS9;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B11', type is buried
_LC3_B11 = LCELL( _EQ012);
_EQ012 = _LC3_B13 & REGIS10;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:135' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B11', type is buried
_LC5_B11 = LCELL( _EQ013);
_EQ013 = _LC3_B13 & REGIS10 & REGIS11;
-- Node name is '|LPM_ADD_SUB:171|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B11', type is buried
_LC7_B11 = LCELL( _EQ014);
_EQ014 = _LC3_B13 & REGIS10 & REGIS11 & REGIS12;
Project Information e:\mydds\dds.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 14,166K
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