📄 sin.rpt
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** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
69 - - A -- OUTPUT 0 1 0 0 q0
6 - - A -- OUTPUT 0 1 0 0 q1
9 - - A -- OUTPUT 0 1 0 0 q2
8 - - A -- OUTPUT 0 1 0 0 q3
22 - - C -- OUTPUT 0 1 0 0 q4
7 - - A -- OUTPUT 0 1 0 0 q5
14 - - B -- OUTPUT 0 1 0 0 q6
10 - - A -- OUTPUT 0 1 0 0 q7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\ks\mydds\sin.rpt
sin
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- - 1 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_0
- - 10 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_1
- - 8 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_2
- - 9 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_3
- - 6 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_4
- - 11 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_5
- - 4 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_6
- - 13 A -- MEM_SGMT 8 0 1 0 |LPM_ROM:1|altrom:srom|segment0_7
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\ks\mydds\sin.rpt
sin
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 0/ 48( 0%) 3/16( 18%) 6/16( 37%) 0/16( 0%)
B: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\ks\mydds\sin.rpt
sin
** EQUATIONS **
ADDRESS0 : INPUT;
ADDRESS1 : INPUT;
ADDRESS2 : INPUT;
ADDRESS3 : INPUT;
ADDRESS4 : INPUT;
ADDRESS5 : INPUT;
ADDRESS6 : INPUT;
ADDRESS7 : INPUT;
CLK : INPUT;
-- Node name is 'q0'
-- Equation name is 'q0', type is output
q0 = _EC1_A;
-- Node name is 'q1'
-- Equation name is 'q1', type is output
q1 = _EC10_A;
-- Node name is 'q2'
-- Equation name is 'q2', type is output
q2 = _EC8_A;
-- Node name is 'q3'
-- Equation name is 'q3', type is output
q3 = _EC9_A;
-- Node name is 'q4'
-- Equation name is 'q4', type is output
q4 = _EC6_A;
-- Node name is 'q5'
-- Equation name is 'q5', type is output
q5 = _EC11_A;
-- Node name is 'q6'
-- Equation name is 'q6', type is output
q6 = _EC4_A;
-- Node name is 'q7'
-- Equation name is 'q7', type is output
q7 = _EC13_A;
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_0' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC1_A', type is memory
_EC1_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_1' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC10_A', type is memory
_EC10_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_2' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC8_A', type is memory
_EC8_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_3' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC9_A', type is memory
_EC9_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_4' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC6_A', type is memory
_EC6_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_5' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC11_A', type is memory
_EC11_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_6' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC4_A', type is memory
_EC4_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
-- Node name is '|LPM_ROM:1|altrom:srom|segment0_7' from file "altrom.tdf" line 92, column 11
-- Equation name is '_EC13_A', type is memory
_EC13_A = MEMORY_SEGMENT( VCC, GLOBAL( CLK), VCC, GND, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, ADDRESS0, ADDRESS1, ADDRESS2, ADDRESS3, ADDRESS4, ADDRESS5, ADDRESS6, ADDRESS7, VCC, VCC, VCC, VCC, VCC, VCC);
Project Information e:\ks\mydds\sin.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:01
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 16,641K
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