sparc.md

这是完整的gcc源代码

  if (GET_CODE (operands[2]) == CONST_DOUBLE
      || GET_CODE (operands[3]) == CONST_DOUBLE)
    make_f0_contain_0 (2);

  if (GET_CODE (operands[2]) == CONST_DOUBLE)
    output_asm_insn (\"fcmped %%f0,%3\;nop\", operands);
  else if (GET_CODE (operands[3]) == CONST_DOUBLE)
    output_asm_insn (\"fcmped %2,%%f0\;nop\", operands);
  else output_asm_insn (\"fcmped %2,%3\;nop\", operands);
  return output_scc_insn (GET_CODE (operands[1]), operands[0]);
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(match_operator 1 "eq_or_neq"
			[(match_operand:DF 2 "general_operand" "f")
			 (const_int 0)]))]
  ""
  "*
{
  CC_STATUS_INIT;
  cc_status.value1 = operands[0];
  cc_status.flags |= CC_IN_FCCR;

  make_f0_contain_0 (2);
  output_asm_insn (\"fcmped %2,%%f0\;nop\", operands);
  return output_scc_insn (GET_CODE (operands[1]), operands[0]);
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r,r")
	(match_operator 1 "eq_or_neq"
			[(compare (match_operand:SF 2 "general_operand" "f,fG")
				  (match_operand:SF 3 "general_operand" "G,f"))
			 (const_int 0)]))]
  ""
  "*
{
  CC_STATUS_INIT;
  cc_status.value1 = operands[0];
  cc_status.flags |= CC_IN_FCCR;

  if (GET_CODE (operands[2]) == CONST_DOUBLE
      || GET_CODE (operands[3]) == CONST_DOUBLE)
    make_f0_contain_0 (1);

  if (GET_CODE (operands[2]) == CONST_DOUBLE)
    output_asm_insn (\"fcmpes %%f0,%3\;nop\", operands);
  else if (GET_CODE (operands[3]) == CONST_DOUBLE)
    output_asm_insn (\"fcmpes %2,%%f0\;nop\", operands);
  else output_asm_insn (\"fcmpes %2,%3\;nop\", operands);
  return output_scc_insn (GET_CODE (operands[1]), operands[0]);
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(match_operator 1 "eq_or_neq"
			[(match_operand:SF 2 "general_operand" "f")
			 (const_int 0)]))]
  ""
  "*
{
  CC_STATUS_INIT;
  cc_status.value1 = operands[0];
  cc_status.flags |= CC_IN_FCCR;

  make_f0_contain_0 (1);
  output_asm_insn (\"fcmpes %2,%%f0\;nop\", operands);
  return output_scc_insn (GET_CODE (operands[1]), operands[0]);
}")

;; These control RTL generation for conditional jump insns
;; and match them for register allocation.

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"be %l0\;nop\", \"be %l0\;nop\", \"fbe %l0\;nop\");
}")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"bne %l0\;nop\", \"bne %l0\;nop\", \"fbne %l0\;nop\");
}")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"bg %l0\;nop\", 0, \"fbg %l0\;nop\");
}")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  if (cc_prev_status.flags & CC_IN_FCCR)
    abort ();
  return \"bgu %l0\;nop\";
}")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"bl %l0\;nop\", \"bneg %l0\;nop\", \"fbl %l0\;nop\");
}")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  if (cc_prev_status.flags & CC_IN_FCCR)
    abort ();
  return \"blu %l0\;nop\";
}")

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"bge %l0\;nop\", \"bpos %l0\;nop\", \"fbge %l0\;nop\");
}")

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  if (cc_prev_status.flags & CC_IN_FCCR)
    abort ();
  return \"bgeu %l0\;nop\";
}")

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  OUTPUT_JUMP (\"ble %l0\;nop\", 0, \"fble %l0\;nop\");
}")

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  if (cc_prev_status.flags & CC_IN_FCCR)
    abort ();
  return \"bleu %l0\;nop\";
}")

;; This matches inverted jump insns for register allocation.

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 1 "" ""))))]
  ""
  "*
{
  if (cc_prev_status.flags & CC_NO_OVERFLOW)
    {
      if (GET_CODE (operands[0]) == GT || GET_CODE (operands[0]) == LE)
	/* These two conditions can't ignore overflow,
	   so reinsert the deleted test instruction.  */
	return 0;
      return \"b%U0 %l1\;nop\";
    }
  if (cc_prev_status.flags & CC_IN_FCCR)
    return \"fb%F0 %l1\;nop\";
  return \"b%N0 %l1\;nop\";
}")

;; Move instructions

(define_insn "swapsi"
  [(set (match_operand:SI 0 "general_operand" "r,rm")
	(match_operand:SI 1 "general_operand" "m,r"))
   (set (match_dup 1) (match_dup 0))]
  ""
  "*
{
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	output_asm_insn (\"set %a1,%%g1\", operands),
	operands[1] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 1)),
	cc_status.flags &= ~CC_KNOW_HI_G1;
      output_asm_insn (\"swap %1,%0\", operands);
    }
  if (REG_P (operands[0]))
    {
      if (REGNO (operands[0]) == REGNO (operands[1]))
	return \"\";
      return \"xor %0,%1,%0\;xor %1,%0,%1\;xor %0,%1,%0\";
    }
  if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    {
      output_asm_insn (\"set %a0,%%g1\", operands);
      operands[0] = gen_rtx (MEM, SImode, gen_rtx (REG, SImode, 1));
      cc_status.flags &= ~CC_KNOW_HI_G1;
    }
  return \"swap %0,%1\";
}")

(define_insn "movsi"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
	(match_operand:SI 1 "general_operand" "rmif,rJ"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	return output_store (operands);
      return \"st %r1,%0\";
    }
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	return output_load_fixed (operands);
      return \"ld %1,%0\";
    }
  if (FP_REG_P (operands[1]))
    return \"st %r1,[%%fp-4]\;ld [%%fp-4],%0\";
  if (REG_P (operands[1])
      || (GET_CODE (operands[1]) == CONST_INT
	  && SMALL_INT (operands[1])))
    return \"mov %1,%0\";
  if (GET_CODE (operands[1]) == CONST_INT
      && (INTVAL (operands[1]) & 0x3ff) == 0)
    return \"sethi %%hi(%1),%0\";
  return \"sethi %%hi(%1),%0\;or %%lo(%1),%0,%0\";
}")

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r,m")
	(match_operand:HI 1 "general_operand" "rmi,rJ"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	return output_store (operands);
      return \"sth %r1,%0\";
    }
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	return output_load_fixed (operands);
      return \"ldsh %1,%0\";
    }
  if (REG_P (operands[1])
      || (GET_CODE (operands[1]) == CONST_INT
	  && SMALL_INT (operands[1])))
    return \"mov %1,%0\";
  return \"sethi %%hi(%1),%0\;or %%lo(%1),%0,%0\";
}")

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r,m")
	(match_operand:QI 1 "general_operand" "rmi,rJ"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	return output_store (operands);
      return \"stb %r1,%0\";
    }
  if (GET_CODE (operands[1]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
	return output_load_fixed (operands);
      return \"ldsb %1,%0\";
    }
  if (REG_P (operands[1])
      || (GET_CODE (operands[1]) == CONST_INT
	  && SMALL_INT (operands[1])))
    return \"mov %1,%0\";
  return \"sethi %%hi(%1),%0\;or %%lo(%1),%0,%0\";
}")

;; The definition of this insn does not really explain what it does,
;; but it should suffice
;; that anything generated as this insn will be recognized as one
;; and that it won't successfully combine with anything.
(define_expand "movstrsi"
  [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
		   (mem:BLK (match_operand:BLK 1 "general_operand" "")))
	      (use (match_operand:SI 2 "arith32_operand" ""))
	      (use (match_operand:SI 3 "immediate_operand" ""))
	      (clobber (match_dup 4))
	      (clobber (match_dup 0))
	      (clobber (match_dup 1))])]
  ""
  "
{
  operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
  operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
  operands[4] = gen_reg_rtx (SImode);
}")

(define_insn ""
  [(set (mem:BLK (match_operand:SI 0 "register_operand" "r"))
	(mem:BLK (match_operand:SI 1 "register_operand" "r")))
   (use (match_operand:SI 2 "arith32_operand" "rn"))
   (use (match_operand:SI 3 "immediate_operand" "i"))
   (clobber (match_operand:SI 4 "register_operand" "=r"))
   (clobber (match_operand:SI 5 "register_operand" "=0"))
   (clobber (match_operand:SI 6 "register_operand" "=1"))]
  ""
  "* return output_block_move (operands);")

;; Floating point move insns

;; This pattern forces (set (reg:DF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movdf pattern.
(define_insn ""
  [(set (match_operand:DF 0 "general_operand" "=r,f,o")
	(match_operand:DF 1 "" "mG,m,G"))]
  "GET_CODE (operands[1]) == CONST_DOUBLE"
  "*
{
  if (FP_REG_P (operands[0]))
    return output_fp_move_double (operands);
  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == REG)
    {
      operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
      return \"mov %%g0,%0\;mov %%g0,%1\";
    }
  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == MEM)
    {
      if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
	{
	  if (! ((cc_prev_status.flags & CC_KNOW_HI_G1)
		 && XEXP (operands[0], 0) == cc_prev_status.mdep))
	    {
	      cc_status.flags |= CC_KNOW_HI_G1;
	      cc_status.mdep = XEXP (operands[0], 0);
	      output_asm_insn (\"sethi %%hi(%m0),%%g1\", operands);
	    }
	  return \"st %%g0,[%%g1+%%lo(%%m0)]\;st %%g0,[%%g1+%%lo(%%m0)+4]\";
	}
      operands[1] = adj_offsettable_operand (operands[0], 4);
      return \"st %%g0,%0\;st %%g0,%1\";
    }
  return output_move_double (operands);
}")

(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=rm,&r,?f,?rm")
	(match_operand:DF 1 "general_operand" "r,m,rfm,f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    return output_load_floating (operands);

  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=rm,&r,?f,?rm")
	(match_operand:DI 1 "general_operand" "r,mi,rfm,f"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
    return output_load_fixed (operands);

  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
    return output_fp_move_double (operands);
  return output_move_double (operands);
}")

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=rf,m")
	(match_operand:SF 1 "general_operand" "rfm,rf"))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM
      && CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
    return output_store (operands);
  if (GET_CODE (operands[1]) == MEM