tahoe.md

这是完整的gcc源代码

    }
}")


; extendsfdf2 tahoe uses the fpp accumulator to do the extension.
; It takes a float and loads it up directly as a double.

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "register_operand" "=a")
	(float_extend:DF (match_operand:SF 1 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"ldfd %1\";
}")


; movz works fine from memory but not from register for the same reasons
; the cvt instructions don't work right.  So we use the normal instruction
; from memory and we use an and to simulate it from register.  This is faster
; than pulling it off the stack.

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
	(zero_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"movzwl %1,%0\";
    case 1:
      return \"andl3 $0xffff,%1,%0\";
    }
}")


; movz works fine from memory but not from register for the same reasons
; the cvt instructions don't work right.  So we use the normal instruction
; from memory and we use an and to simulate it from register.  This is faster
; than pulling it off the stack.

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=g,?=g")
	(zero_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"movzbw %1,%0\";
    case 1:
      return \"andw3 $0xff,%1,%0\";
    }
}")


; movz works fine from memory but not from register for the same reasons
; the cvt instructions don't work right.  So we use the normal instruction
; from memory and we use an and to simulate it from register.  This is faster
; than pulling it off the stack.

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
	(zero_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"movzbl %1,%0\";
    case 1:
      return \"andl3 $0xff,%1,%0\";
    }
}")


(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jeql %l0")


(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jneq %l0")


(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jgtr %l0")


(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jgtru %l0")


(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jlss %l0")


(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jlssu %l0")


(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jgeq %l0")


(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jgequ %l0")


(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jleq %l0")


(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "jlequ %l0")


; GCC does not account for register mask/argc longword.  Thus the number
; for the call = number bytes for args + 4

(define_insn "call"
  [(call (match_operand:QI 0 "general_operand" "g")
	 (match_operand:QI 1 "general_operand" "g"))]
  ""
  "*
{
  operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 4));
  return \"calls %1,%0\";
}")


; GCC does not account for register mask/argc longword.  Thus the number
; for the call = number bytes for args + 4

(define_insn "call_value"
  [(set (match_operand 0 "" "=g")
	(call (match_operand:QI 1 "general_operand" "g")
	      (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 4));
  return \"calls %2,%1\";
}")


(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")


(define_insn "return"
  [(return)]
  ""
  "ret")


; casesi, extracted from the vax code.  The instructions are
; very similar.  Tahoe requires that the table be word aligned.  GCC
; places the table immediately after, thus the alignment directive.

(define_insn "casesi"
  [(set (pc)
	(if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")
				    (match_operand:SI 1 "general_operand" "g"))
			  (match_operand:SI 2 "general_operand" "g"))
		      (plus:SI (sign_extend:SI
				(mem:HI (plus:SI (pc)
						 (minus:SI (match_dup 0)
							   (match_dup 1)))))
			       (label_ref:SI (match_operand 3 "" "")))
		      (pc)))]
  ""
  "casel %0,%1,%2\;.align %@")


(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jbr %l0")


;; This is the list of all the non-standard insn patterns


; This is used to access the address of a byte.  This is similar to
; movqi, but the second operand had to be "address_operand" type, so
; it had to be an unnamed one.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(match_operand:QI 1 "address_operand" "p"))]
  ""
  "*
{
  if (push_operand (operands[0], SImode))
    return \"pushab %a1\";
  return \"movab %a1,%0\";
}")

; This is used to access the address of a word.  This is similar to
; movhi, but the second operand had to be "address_operand" type, so
; it had to be an unnamed one.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(match_operand:HI 1 "address_operand" "p"))]
  ""
  "*
{
  if (push_operand (operands[0], SImode))
    return \"pushaw %a1\";
  return \"movaw %a1,%0\";
}")

; This is used to access the address of a long.  This is similar to
; movsi, but the second operand had to be "address_operand" type, so
; it had to be an unnamed one.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(match_operand:SI 1 "address_operand" "p"))]
  ""
  "*
{
  if (push_operand (operands[0], SImode))
    return \"pushal %a1\";
  return \"moval %a1,%0\";
}")

; The tahoe doesn't have an 8 byte indexed move address command
; and GCC needs it.  To work around it, double the index (%2) and
; then use the 4 byte indexed move address command.
;
;(define_insn ""
;  [(set (match_operand:SI 0 "general_operand" "=g")
;	(plus:SI (match_operand:SI 1 "general_operand" "g")
;		 (mult:SI (match_operand:SI 2 "register_operand" "r")
;			  (const_int 8))))]
;  ""
;  "*
;{
;  if (GET_CODE (operands[0]) == REG &&
;      REGNO (operands[0]) == REGNO (operands[2])) {
;	return \"shll $3,%2,%2\;addl3 %1,%2,%0\";
;  } else {
;	return \"shll $3,%2,%2\;addl3 %1,%2,%0\;shrl $3,%2,%2\"; }
;}")


; Bit test longword instruction, same as vax.

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "general_operand" "g")
		(match_operand:SI 1 "general_operand" "g")))]
  ""
  "bitl %0,%1")


; Bit test word instructions, same as vax.

(define_insn ""
  [(set (cc0)
	(and:HI (match_operand:HI 0 "general_operand" "g")
		(match_operand:HI 1 "general_operand" "g")))]
  ""
  "bitw %0,%1")


; Bit test instructions, same as vax.

(define_insn ""
  [(set (cc0)
	(and:QI (match_operand:QI 0 "general_operand" "g")
		(match_operand:QI 1 "general_operand" "g")))]
  ""
  "bitb %0,%1")


; bne counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jneq %l0")


; beq counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jeql %l0")


; ble counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jleq %l0")


; bleu counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jlequ %l0")


; bge counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jgeq %l0")


; bgeu counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jgequ %l0")


; blt counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jlss %l0")


; bltu counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jlssu %l0")


; bgt counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jgtr %l0")


; bgtu counterpart.  In case GCC reverses the conditional.

(define_insn ""
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "jgtru %l0")


; casesi alternate form as found in vax code.  This form is to
; compensate for the table's offset being no distance (0 displacement)

(define_insn ""
  [(set (pc)
	(if_then_else (le (match_operand:SI 0 "general_operand" "g")
			  (match_operand:SI 1 "general_operand" "g"))
		      (plus:SI (sign_extend:SI
				(mem:HI (plus:SI (pc)
						 (minus:SI (match_dup 0)
							   (const_int 0)))))
			       (label_ref:SI (match_operand 3 "" "")))
		      (pc)))]
  ""
  "casel %0,$0,%1\;.align %@")


; casesi alternate form as found in vax code.  Another form to
; compensate for the table's offset being no distance (0 displacement)

(define_insn ""
  [(set (pc)
	(if_then_else (le (match_operand:SI 0 "general_operand" "g")
			  (match_operand:SI 1 "general_operand" "g"))
		      (plus:SI (sign_extend:SI
				(mem:HI (plus:SI (pc)
						 (match_dup 0))))
			       (label_ref:SI (match_operand 3 "" "")))
		      (pc)))]
  ""
  "casel %0,$0,%1 \;.align %@")