tahoe.md

这是完整的gcc源代码

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ior:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "orl3 %2,%1,%0")


(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(ior:HI (match_operand:HI 1 "general_operand" "g")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "orw3 %2,%1,%0")


(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(ior:QI (match_operand:QI 1 "general_operand" "g")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "orb3 %2,%1,%0")


(define_insn "xorsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(xor:SI (match_operand:SI 1 "general_operand" "g")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "xorl3 %1,%2,%0")


(define_insn "xorhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(xor:HI (match_operand:HI 1 "general_operand" "g")
		(match_operand:HI 2 "general_operand" "g")))]
  ""
  "xorw3 %1,%2,%0")


(define_insn "xorqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(xor:QI (match_operand:QI 1 "general_operand" "g")
		(match_operand:QI 2 "general_operand" "g")))]
  ""
  "xorb3 %1,%2,%0")


; Shifts on the tahoe are expensive, so try to do an add instead.

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ashift:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
    {
      CC_STATUS_INIT;
      return \"addl2 %0,%0\";
    }
  return \"shal %2,%1,%0\";
}")


(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "shar %2,%1,%0")


; Shifts are very expensive, so try to do an add if possible.

(define_insn "lshlsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(lshift:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "*
{
  if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1]))
    {
      CC_STATUS_INIT;
      return \"addl2 %0,%0\";
    }
  return \"shll %2,%1,%0\";
}")


(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:QI 2 "general_operand" "g")))]
  ""
  "shrl %2,%1,%0")


(define_insn "negsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(neg:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "mnegl %1,%0")


(define_insn "neghi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(neg:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "mnegw %1,%0")


(define_insn "negqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(neg:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "mnegb %1,%0")


; negsf2 can only negate the value already in the fpp accumulator.
; The value remains in the fpp accumulator.  No flags are set.

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=a,=a")
	(neg:SF (match_operand:SF 1 "register_operand" "a,g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  switch (which_alternative)
    {
    case 0:
      return \"negf\";
    case 1:
      return \"lnf %1\";
    }
}")


; negdf2 can only negate the value already in the fpp accumulator.
; The value remains in the fpp accumulator.  No flags are set.

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=a,=a")
	(neg:DF (match_operand:DF 1 "register_operand" "a,g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  switch (which_alternative)
    {
    case 0:
      return \"negd\";
    case 1:
      return \"lnd %1\";
    }
}")


; sqrtsf2 tahoe can calculate the square root of a float in the
; fpp accumulator.  The answer remains in the fpp accumulator.  No
; flags are set by this function.

(define_insn "sqrtsf2"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"sqrtf\";
}")


; ffssi2 tahoe instruction gives one less than GCC desired result for
; any given input.  So the increment is necessary here.

(define_insn "ffssi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ffs:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "ffs %1,%0\;incl %0")


(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(not:SI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "mcoml %1,%0")


(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(not:HI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "mcomw %1,%0")


(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(not:QI (match_operand:QI 1 "general_operand" "g")))]
  ""
  "mcomb %1,%0")


; cmpsi works fine, but due to microcode problems, the tahoe doesn't
; properly compare hi's and qi's.  Leaving them out seems to be acceptable
; to the compiler, so they were left out.  Compares of the stack are
; possible, though.

;; Put cmpsi first among compare insns so it matches two CONST_INT operands.

(define_insn "cmpsi"
  [(set (cc0)
	(compare (match_operand:SI 0 "general_operand" "g")
	         (match_operand:SI 1 "general_operand" "g")))]
  ""
  "cmpl %0,%1")


; cmpsf similar to vax, but first operand is expected to be in the
; fpp accumulator.

(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "register_operand" "a")
	         (match_operand:SF 1 "general_operand" "g")))]
  ""
  "cmpf %1")


; cmpdf similar to vax, but first operand is expected to be in the
; fpp accumulator.  Immediate doubles not allowed.

(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "a")
	         (match_operand:DF 1 "general_operand" "rm")))]
  ""
  "cmpd %1")


;; Put tstsi first among test insns so it matches a CONST_INT operand.

(define_insn "tstsi"
  [(set (cc0)
	(match_operand:SI 0 "general_operand" "g"))]
  ""
  "tstl %0")


; Small tests from memory are normal, but testing from registers don't
; expand the data properly.  So test in this case does a convert and tests
; the new register data from the stack.

(define_insn "tsthi"
  [(set (cc0)
	(match_operand:HI 0 "general_operand" "m,?r"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"tstw %0\";
    case 1:
      return \"pushl %0\;cvtwl 2(sp),(sp)\;tstl (sp)+\";
    }
}")


; Small tests from memory are normal, but testing from registers don't
; expand the data properly.  So test in this case does a convert and tests
; the new register data from the stack.

(define_insn "tstqi"
  [(set (cc0)
	(match_operand:QI 0 "general_operand" "m,?r"))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"tstb %0\";
    case 1:
      return \"pushl %0\;cvtbl 3(sp),(sp)\;tstl (sp)+\";
    }
}")


; tstsf compares a given value to a value already in the fpp accumulator.
; No flags are set by this so ignore them.

(define_insn "tstsf"
  [(set (cc0)
	(match_operand:SF 0 "register_operand" "a"))]
  ""
  "tstf")


; tstdf compares a given value to a value already in the fpp accumulator.
; immediate doubles not allowed.  Flags are ignored after this.

(define_insn "tstdf"
  [(set (cc0)
	(match_operand:DF 0 "register_operand" "a"))]
  ""
  "tstd")


; movstrhi tahoe instruction does not load registers by itself like
; the vax counterpart does.  registers 0-2 must be primed by hand.
; we have loaded the registers in the order: dst, src, count.

(define_insn "movstrhi"
  [(set (match_operand:BLK 0 "general_operand" "p")
	 (match_operand:BLK 1 "general_operand" "p"))
   (use (match_operand:HI 2 "general_operand" "g"))
   (clobber (reg:SI 0))
   (clobber (reg:SI 1))
   (clobber (reg:SI 2))]
  ""
  "movab %0,r1\;movab %1,r0\;movl %2,r2\;movblk")


; floatsisf2 on tahoe converts the long from reg/mem into the fpp
; accumulator.  There are no hi and qi counterparts.  Flags are not
; set correctly here.

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(float:SF (match_operand:SI 1 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"cvlf %1\";
}")


; floatsidf2 on tahoe converts the long from reg/mem into the fpp
; accumulator.  There are no hi and qi counterparts.  Flags are not
; set correctly here.

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "register_operand" "=a")
	(float:DF (match_operand:SI 1 "general_operand" "g")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"cvld %1\";
}")


; fix_truncsfsi2 to convert a float to long, tahoe must have the float
; in the fpp accumulator.  Flags are not set here.

(define_insn "fix_truncsfsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "a"))))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"cvfl %0\";
}")


; fix_truncsfsi2 to convert a double to long, tahoe must have the double
; in the fpp accumulator.  Flags are not set here.

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "a"))))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"cvdl %0\";
}")


(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(truncate:HI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "cvtlw %1,%0")


(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI (match_operand:SI 1 "general_operand" "g")))]
  ""
  "cvtlb %1,%0")


(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI (match_operand:HI 1 "general_operand" "g")))]
  ""
  "cvtwb %1,%0")


; The fpp related instructions don't set flags, so ignore them
; after this instruction.

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "register_operand" "=a")
	(float_truncate:SF (match_operand:DF 1 "register_operand" "0")))]
  ""
  "*
{
  CC_STATUS_INIT;
  return \"cvdf\";
}")


; This monster is to cover for the Tahoe's nasty habit of not extending
; a number if the source is in a register.  (It just moves it!)  Case 0 is
; a normal extend from memory.  Case 1 does the extension from the top of
; the stack.  Extension from the stack doesn't set the flags right since
; the moval changes them.

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
	(sign_extend:SI (match_operand:HI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"cvtwl %1,%0\";
    case 1:
      if (push_operand(operands[0], SImode))
	return \"pushl %1\;cvtwl 2(sp),(sp)\";
      else
	{
	  CC_STATUS_INIT;
	  return \"pushl %1\;cvtwl 2(sp),%0\;moval 4(sp),sp\";
	}
    }
}")


; This monster is to cover for the Tahoe's nasty habit of not extending
; a number if the source is in a register.  (It just moves it!)  Case 0 is
; a normal extend from memory.  Case 1 does the extension from the top of
; the stack.  Extension from the stack doesn't set the flags right since
; the moval changes them.

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=g,?=g")
	(sign_extend:SI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"cvtbl %1,%0\";
    case 1:
      if (push_operand(operands[0], SImode))
	return \"pushl %1\;cvtbl 3(sp),(sp)\";
      else
	{
	  CC_STATUS_INIT;
	  return \"pushl %1\;cvtbl 3(sp),%0\;moval 4(sp),sp\";
	}
    }
}")


; This monster is to cover for the Tahoe's nasty habit of not extending
; a number if the source is in a register.  (It just moves it!)  Case 0 is
; a normal extend from memory.  Case 1 does the extension from the top of
; the stack.  Extension from the stack doesn't set the flags right since
; the moval changes them.

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "general_operand" "=g,?=g")
	(sign_extend:HI (match_operand:QI 1 "general_operand" "m,r")))]
  ""
  "*
{
  switch (which_alternative)
    {
    case 0:
      return \"cvtbw %1,%0\";
    case 1:
      if (push_operand(operands[0], SImode))
	return \"pushl %1\;cvtbw 3(sp),2(sp)\";
      else {
	CC_STATUS_INIT;
	return \"pushl %1\;cvtbw 3(sp),%0\;moval 4(sp),sp\";
      }