pyr.md

这是完整的gcc源代码

  return \"movzhw %1,%0\";
}")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "*
{
  cc_status.flags = CC_NOT_NEGATIVE;
  return \"movzbw %1,%0\";
}")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "*
{
  cc_status.flags = CC_NOT_NEGATIVE;
  return \"movzbw %1,%0\";
}")

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "general_operand" "=&r,m")
	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "rm,r")))]
  ""
  "cvtfd %1,%0")

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "general_operand" "=&r,m")
	(float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "rm,r")))]
  ""
  "cvtdf %1,%0")

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "general_operand" "=&r,m")
	(float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
  ""
  "cvtwf %1,%0")

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "general_operand" "=&r,m")
	(float:DF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
  ""
  "cvtwd %1,%0")

(define_insn "fix_truncsfsi2"
  [(set (match_operand:SI 0 "general_operand" "=&r,m")
	(fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "rm,r"))))]
  ""
  "cvtfw %1,%0")

(define_insn "fix_truncdfsi2"
  [(set (match_operand:SI 0 "general_operand" "=&r,m")
	(fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "rm,r"))))]
  ""
  "cvtdw %1,%0")

;______________________________________________________________________
;
;	Flow Control Patterns.
;______________________________________________________________________

;; Prefer "br" to "jump" for unconditional jumps, since it's faster.
;; (The assembler can manage with out-of-range branches.)

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "br %l0")

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
		      (label_ref (match_operand 1 "" ""))
		      (pc)))]
  ""
  "*
{
  extern int optimize;
  if (optimize)
    switch (GET_CODE (operands[0]))
      {
      case EQ: case NE:
	break;
      case LT: case LE: case GE: case GT:
	if (cc_prev_status.mdep == CC_VALID_FOR_UNSIGNED)
	  return 0;
	break;
      case LTU: case LEU: case GEU: case GTU:
	if (cc_prev_status.mdep != CC_VALID_FOR_UNSIGNED)
	  return 0;
	break;
      }

  return \"b%N0 %l1\";
}")

(define_insn ""
  [(set (pc)
	(if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
		      (pc)
		      (label_ref (match_operand 1 "" ""))))]
  ""
  "*
{
  extern int optimize;
  if (optimize)
    switch (GET_CODE (operands[0]))
      {
      case EQ: case NE:
	break;
      case LT: case LE: case GE: case GT:
	if (cc_prev_status.mdep == CC_VALID_FOR_UNSIGNED)
	  return 0;
	break;
      case LTU: case LEU: case GEU: case GTU:
	if (cc_prev_status.mdep != CC_VALID_FOR_UNSIGNED)
	  return 0;
	break;
      }

  return \"b%C0 %l1\";
}")

(define_insn "call"
  [(call (match_operand:QI 0 "memory_operand" "m")
	 (match_operand:SI 1 "immediate_operand" "n"))]
  ""
  "call %0")

(define_insn "call_value"
  [(set (match_operand 0 "" "=r")
	(call (match_operand:QI 1 "memory_operand" "m")
	      (match_operand:SI 2 "immediate_operand" "n")))]
  ;; Operand 2 not really used on Pyramid architecture.
  ""
  "call %1")

(define_insn "return"
  [(return)]
  ""
  "*
{
  if (get_frame_size () + current_function_pretend_args_size
      + current_function_args_size != 0
      || current_function_calls_alloca)
    {
      int dealloc_size = current_function_pretend_args_size;
      if (current_function_pops_args)
        dealloc_size += current_function_args_size;
      operands[0] = gen_rtx (CONST_INT, VOIDmode, dealloc_size);
      return \"retd %0\";
    }
  else
    return \"ret\";
}")

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jump (%0)")

(define_insn "nop"
  [(const_int 0)]
  ""
  "movw gr0,gr0  # nop")

;______________________________________________________________________
;
;	Peep-hole Optimization Patterns.
;______________________________________________________________________

;; Optimize fullword move followed by a test of the moved value.

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:SI 1 "nonimmediate_operand" "rm"))
   (set (cc0) (match_operand:SI 2 "nonimmediate_operand" "rm"))]
  "rtx_equal_p (operands[2], operands[0])
   || rtx_equal_p (operands[2], operands[1])"
  "*
  cc_status.flags |= CC_NO_OVERFLOW;
  return \"mtstw %1,%0\";
")

;; Same for HI and QI mode move-test as well.

(define_peephole
  [(set (match_operand:HI 0 "register_operand" "=r")
	(match_operand:HI 1 "nonimmediate_operand" "rm"))
   (set (match_operand:SI 2 "register_operand" "=r")
	(sign_extend:SI (match_operand:HI 3 "nonimmediate_operand" "rm")))
   (set (cc0) (match_dup 2))]
  "dead_or_set_p (insn, operands[2])
   && (rtx_equal_p (operands[3], operands[0])
       || rtx_equal_p (operands[3], operands[1]))"
  "*
  cc_status.flags |= CC_NO_OVERFLOW;
  return \"cvthw %1,%0\";
")

(define_peephole
  [(set (match_operand:QI 0 "register_operand" "=r")
	(match_operand:QI 1 "nonimmediate_operand" "rm"))
   (set (match_operand:SI 2 "register_operand" "=r")
	(sign_extend:SI (match_operand:QI 3 "nonimmediate_operand" "rm")))
   (set (cc0) (match_dup 2))]
  "dead_or_set_p (insn, operands[2])
   && (rtx_equal_p (operands[3], operands[0])
       || rtx_equal_p (operands[3], operands[1]))"
  "*
  cc_status.flags |= CC_NO_OVERFLOW;
  return \"cvtbw %1,%0\";
")

;; Optimize loops with an incremented/decremented variable.

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 0)
		 (const_int -1)))
   (set (cc0)
	(compare (match_operand:SI 1 "register_operand" "r")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (set (pc)
	(if_then_else (match_operator:SI 3 "signed_comparison"
			 [(cc0) (const_int 0)])
		      (label_ref (match_operand 4 "" ""))
		      (pc)))]
  "(GET_CODE (operands[2]) == CONST_INT
    ? (unsigned)INTVAL (operands[2]) + 32 >= 64
    : 1) && (rtx_equal_p (operands[0], operands[1])
	     || rtx_equal_p (operands[0], operands[2]))"
  "*
  if (rtx_equal_p (operands[0], operands[1]))
    {
      output_asm_insn (\"dcmpw %2,%0\", operands);
      return \"b%N3 %l4\";
    }
  else
    {
      output_asm_insn (\"dcmpw %1,%0\", operands);
      return \"b%R3 %l4\";
    }
")

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_dup 0)
		 (const_int 1)))
   (set (cc0)
	(compare (match_operand:SI 1 "register_operand" "r")
		 (match_operand:SI 2 "nonmemory_operand" "ri")))
   (set (pc)
	(if_then_else (match_operator:SI 3 "signed_comparison"
			 [(cc0) (const_int 0)])
		      (label_ref (match_operand 4 "" ""))
		      (pc)))]
  "(GET_CODE (operands[2]) == CONST_INT
    ? (unsigned)INTVAL (operands[2]) + 32 >= 64
    : 1) && (rtx_equal_p (operands[0], operands[1])
	     || rtx_equal_p (operands[0], operands[2]))"
  "*
  if (rtx_equal_p (operands[0], operands[1]))
    {
      output_asm_insn (\"icmpw %2,%0\", operands);
      return \"b%N3 %l4\";
    }
  else
    {
      output_asm_insn (\"icmpw %1,%0\", operands);
      return \"b%R3 %l4\";
    }
")

;; Combine two word moves with consecutive operands into one long move.
;; Also combines immediate moves, if the high-order destination operand
;; is loaded with 0 or -1 and the low-order destination operand is loaded
;; with a constant with the same sign.

(define_peephole
  [(set (match_operand:SI 0 "general_operand" "=g")
	(match_operand:SI 1 "general_operand" "g"))
   (set (match_operand:SI 2 "general_operand" "=g")
	(match_operand:SI 3 "general_operand" "g"))]
  "movdi_possible (operands)"
  "*
  output_asm_insn (\"# COMBINE movw %1,%0\", operands);
  output_asm_insn (\"# COMBINE movw %3,%2\", operands);
  movdi_possible (operands);
  if (CONSTANT_P (operands[1]))
    return (swap_operands) ? \"movl %3,%0\" : \"movl %1,%2\";

  return (swap_operands) ? \"movl %1,%0\" : \"movl %3,%2\";
")

;; Optimize certain tests after memory stores.

(define_peephole
  [(set (match_operand 0 "memory_operand" "=m")
	(match_operand 1 "register_operand" "r"))
   (set (match_operand:SI 2 "register_operand" "=r")
	(sign_extend:SI (match_dup 1)))
   (set (cc0)
	(match_dup 2))]
  "dead_or_set_p (insn, operands[2])"
  "*
  cc_status.flags |= CC_NO_OVERFLOW;
  if (GET_MODE (operands[0]) == QImode)
    return \"cvtwb %1,%0\";
  else
    return \"cvtwh %1,%0\";
")

;______________________________________________________________________
;
;	DImode Patterns.
;______________________________________________________________________

(define_expand "extendsidi2"
  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1)
	(match_operand:SI 1 "general_operand" "g"))
   (set (subreg:SI (match_dup 0) 0)
	(subreg:SI (match_dup 0) 1))
   (set (subreg:SI (match_dup 0) 0)
	(ashiftrt:SI (subreg:SI (match_dup 0) 0)
		     (const_int 31)))]
  ""
  "")

(define_insn "adddi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(plus:DI (match_operand:DI 1 "nonmemory_operand" "%0")
		 (match_operand:DI 2 "nonmemory_operand" "rF")))]
  ""
  "*
{
  rtx xoperands[2];
  CC_STATUS_INIT;
  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  if (REG_P (operands[2]))
    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  else
    {
      xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
			      CONST_DOUBLE_LOW (operands[2]));
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     CONST_DOUBLE_HIGH (operands[2]));
    }
  output_asm_insn (\"addw %1,%0\", xoperands);
  return \"addwc %2,%0\";
}")

(define_insn "subdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(minus:DI (match_operand:DI 1 "register_operand" "0")
		  (match_operand:DI 2 "nonmemory_operand" "rF")))]
  ""
  "*
{
  rtx xoperands[2];
  CC_STATUS_INIT;
  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  if (REG_P (operands[2]))
    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  else
    {
      xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
			      CONST_DOUBLE_LOW (operands[2]));
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     CONST_DOUBLE_HIGH (operands[2]));
    }
  output_asm_insn (\"subw %1,%0\", xoperands);
  return \"subwb %2,%0\";
}")

(define_insn "iordi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ior:DI (match_operand:DI 1 "nonmemory_operand" "%0")
		(match_operand:DI 2 "nonmemory_operand" "rF")))]
  ""
  "*
{
  rtx xoperands[2];
  CC_STATUS_INIT;
  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  if (REG_P (operands[2]))
    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  else
    {
      xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
			      CONST_DOUBLE_LOW (operands[2]));
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     CONST_DOUBLE_HIGH (operands[2]));
    }
  output_asm_insn (\"orw %1,%0\", xoperands);
  return \"orw %2,%0\";
}")

(define_insn "anddi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(and:DI (match_operand:DI 1 "nonmemory_operand" "%0")
		(match_operand:DI 2 "nonmemory_operand" "rF")))]
  ""
  "*
{
  rtx xoperands[2];
  CC_STATUS_INIT;
  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  if (REG_P (operands[2]))
    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  else
    {
      xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
			      CONST_DOUBLE_LOW (operands[2]));
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     CONST_DOUBLE_HIGH (operands[2]));
    }
  output_asm_insn (\"andw %1,%0\", xoperands);
  return \"andw %2,%0\";
}")

(define_insn "xordi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(xor:DI (match_operand:DI 1 "nonmemory_operand" "%0")
		(match_operand:DI 2 "nonmemory_operand" "rF")))]
  ""
  "*
{
  rtx xoperands[2];
  CC_STATUS_INIT;
  xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
  if (REG_P (operands[2]))
    xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
  else
    {
      xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
			      CONST_DOUBLE_LOW (operands[2]));
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     CONST_DOUBLE_HIGH (operands[2]));
    }
  output_asm_insn (\"xorw %1,%0\", xoperands);
  return \"xorw %2,%0\";
}")

;;- Local variables:
;;- mode:emacs-lisp
;;- comment-start: ";;- "
;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
;;- eval: (modify-syntax-entry ?] ")[")
;;- eval: (modify-syntax-entry ?{ "(}")
;;- eval: (modify-syntax-entry ?} "){")
;;- End: