pyr.md

这是完整的gcc源代码

	(mod:SI (match_operand:SI 1 "register_operand" "0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "modw %2,%0")

(define_insn "umodsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(umod:SI (match_operand:SI 1 "register_operand" "0")
		 (match_operand:SI 2 "general_operand" "g")))]
  ""
  "umodw %2,%0")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
  ""
  "mnegw %1,%0")

(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
  ""
  "mcomw %1,%0")

(define_insn "abssi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(abs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
  ""
  "mabsw %1,%0")

;______________________________________________________________________
;
;	Floating-point Arithmetic.
;______________________________________________________________________

(define_insn "adddf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(plus:DF (match_operand:DF 1 "register_operand" "%0")
		 (match_operand:DF 2 "register_operand" "r")))]
  ""
  "addd %2,%0")

(define_insn "addsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(plus:SF (match_operand:SF 1 "register_operand" "%0")
		 (match_operand:SF 2 "register_operand" "r")))]
  ""
  "addf %2,%0")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(minus:DF (match_operand:DF 1 "register_operand" "0")
		  (match_operand:DF 2 "register_operand" "r")))]
  ""
  "subd %2,%0")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(minus:SF (match_operand:SF 1 "register_operand" "0")
		  (match_operand:SF 2 "register_operand" "r")))]
  ""
  "subf %2,%0")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(mult:DF (match_operand:DF 1 "register_operand" "%0")
		 (match_operand:DF 2 "register_operand" "r")))]
  ""
  "muld %2,%0")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(mult:SF (match_operand:SF 1 "register_operand" "%0")
		 (match_operand:SF 2 "register_operand" "r")))]
  ""
  "mulf %2,%0")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(div:DF (match_operand:DF 1 "register_operand" "0")
		(match_operand:DF 2 "register_operand" "r")))]
  ""
  "divd %2,%0")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(div:SF (match_operand:SF 1 "register_operand" "0")
		(match_operand:SF 2 "register_operand" "r")))]
  ""
  "divf %2,%0")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(neg:DF (match_operand:DF 1 "register_operand" "r")))]
  ""
  "mnegd %1,%0")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(neg:SF (match_operand:SF 1 "register_operand" "r")))]
  ""
  "mnegf %1,%0")

(define_insn "absdf2"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(abs:DF (match_operand:DF 1 "register_operand" "r")))]
  ""
  "mabsd %1,%0")

(define_insn "abssf2"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(abs:SF (match_operand:SF 1 "register_operand" "r")))]
  ""
  "mabsf %1,%0")

;______________________________________________________________________
;
;	Logical and Shift Instructions.
;______________________________________________________________________

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "general_operand" "%r")
		(match_operand:SI 1 "general_operand" "g")))]
  ""
  "*
{
  cc_status.flags |= CC_NO_OVERFLOW;
  return \"bitw %1,%0\";
}")

(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(and:SI (match_operand:SI 1 "general_operand" "%0,r")
		(match_operand:SI 2 "general_operand" "g,K")))]
  ""
  "*
{
  if (which_alternative == 0)
    return \"andw %2,%0\";

  cc_status.flags = CC_NOT_NEGATIVE;
  return (INTVAL (operands[2]) == 255
	  ? \"movzbw %1,%0\" : \"movzhw %1,%0\");
}")

(define_insn "andcbsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "0")
		(not:SI (match_operand:SI 2 "general_operand" "g"))))]
  ""
  "bicw %2,%0")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
		(match_operand:SI 2 "register_operand" "0")))]
  ""
  "bicw %1,%0")

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "orw %2,%0")

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_operand:SI 1 "general_operand" "%0")
		(match_operand:SI 2 "general_operand" "g")))]
  ""
  "xorw %2,%0")

; The arithmetic left shift instructions work strangely on pyramids.
; They fail to modify the sign bit.  Therefore, use logic shifts.

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "0")
		   (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"lshlw %2,%0\", operands[2], 32); ")

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
		     (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"ashrw %2,%0\", operands[2], 32); ")

(define_insn "ashrdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
	(ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
		     (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"ashrl %2,%0\", operands[2], 64); ")

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
		     (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"lshrw %2,%0\", operands[2], 32); ")

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(rotate:SI (match_operand:SI 1 "register_operand" "0")
		   (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"rotlw %2,%0\", operands[2], 32); ")

(define_insn "rotrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(rotatert:SI (match_operand:SI 1 "register_operand" "0")
		     (match_operand:SI 2 "general_operand" "rnm")))]
  ""
  "* return output_shift (\"rotrw %2,%0\", operands[2], 32); ")

;______________________________________________________________________
;
;	Fixed and Floating Moves.
;______________________________________________________________________

;; If the destination is a memory operand, indexed source operands are
;; disallowed.  Big DImode constants are always loaded into a reg pair,
;; although offsetable memory addresses really could be dealt with.

(define_insn ""
  [(set (match_operand:DI 0 "memory_operand" "=m")
	(match_operand:DI 1 "nonindexed_operand" "gF"))]
  "(GET_CODE (operands[1]) == CONST_DOUBLE
     ? ((CONST_DOUBLE_HIGH (operands[1]) == 0
	 && CONST_DOUBLE_LOW (operands[1]) >= 0)
	|| (CONST_DOUBLE_HIGH (operands[1]) == -1
	    && CONST_DOUBLE_LOW (operands[1]) < 0))
     : 1)"
  "*
{
  if (GET_CODE (operands[1]) == CONST_DOUBLE)
    operands[1] = gen_rtx (CONST_INT, VOIDmode,
				      CONST_DOUBLE_LOW (operands[1]));
  return \"movl %1,%0\";
}")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=r")
	(match_operand:DI 1 "general_operand" "gF"))]
  ""
  "* return output_move_double (operands); ")

;; If the destination is a memory address, indexed source operands are
;; disallowed.

(define_insn ""
  [(set (match_operand:SI 0 "memory_operand" "=m")
	(match_operand:SI 1 "nonindexed_operand" "g"))]
  ""
  "movw %1,%0")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movsi"
  [(set (match_operand:SI 0 "general_operand" "=r")
	(match_operand:SI 1 "general_operand" "g"))]
  ""
  "movw %1,%0")

;; If the destination is a memory address, indexed source operands are
;; disallowed.

(define_insn ""
  [(set (match_operand:HI 0 "memory_operand" "=m")
	(match_operand:HI 1 "nonindexed_operand" "g"))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"cvtwh %1,%0\";		/* reg -> mem */
  else
    return \"movh %1,%0\";		/* mem imm -> mem */
}")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movhi"
  [(set (match_operand:HI 0 "general_operand" "=r")
	(match_operand:HI 1 "general_operand" "g"))]
  ""
  "*
{
  if (GET_CODE (operands[1]) != MEM)
    return \"movw %1,%0\";		/* reg imm -> reg  */
  return \"cvthw %1,%0\";		/* mem -> reg */
}")

;; If the destination is a memory address, indexed source operands are
;; disallowed.

(define_insn ""
  [(set (match_operand:QI 0 "memory_operand" "=m")
	(match_operand:QI 1 "nonindexed_operand" "g"))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"cvtwb %1,%0\";		/* reg -> mem */
  else
    return \"movb %1,%0\";		/* mem imm -> mem */
}")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movqi"
  [(set (match_operand:QI 0 "general_operand" "=r")
	(match_operand:QI 1 "general_operand" "g"))]
  ""
  "*
{
  if (GET_CODE (operands[1]) != MEM)
    return \"movw %1,%0\";		/* reg imm -> reg  */
  return \"cvtbw %1,%0\";		/* mem -> reg */
}")

;; If the destination is a memory address, indexed source operands are
;; disallowed.

(define_insn ""
  [(set (match_operand:DF 0 "memory_operand" "=m")
	(match_operand:DF 1 "nonindexed_operand" "g"))]
  "GET_CODE (operands[1]) != CONST_DOUBLE"
  "movl %1,%0")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=r")
	(match_operand:DF 1 "general_operand" "gF"))]
  ""
  "* return output_move_double (operands); ")

;; If the destination is a memory address, indexed source operands are
;; disallowed.

(define_insn ""
  [(set (match_operand:SF 0 "memory_operand" "=m")
	(match_operand:SF 1 "nonindexed_operand" "g"))]
  ""
  "movw %1,%0")

;; Force the destination to a register, so all source operands are allowed.

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=r")
	(match_operand:SF 1 "general_operand" "g"))]
  ""
  "movw %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:QI 1 "address_operand" "p"))]
  ""
  "*
{
  forget_cc_if_dependent (operands[0]);
  return \"mova %a1,%0\";
}")

;______________________________________________________________________
;
;	Conversion patterns.
;______________________________________________________________________

;; The trunc patterns are used only when non compile-time constants are used.

(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "register_operand" "=r")
	(truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
  ""
  "*
{
  if (REG_P (operands[0]) && REG_P (operands[1])
      && REGNO (operands[0]) == REGNO (operands[1]))
    {
      cc_status = cc_prev_status;
      return \"\";
    }
  forget_cc_if_dependent (operands[0]);
  return \"movw %1,%0\";
}")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
  ""
  "*
{
  if (REG_P (operands[0]) && REG_P (operands[1])
      && REGNO (operands[0]) == REGNO (operands[1]))
    {
      cc_status = cc_prev_status;
      return \"\";
    }
  forget_cc_if_dependent (operands[0]);
  return \"movw %1,%0\";
}")

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
	(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm,r")))]
  ""
  "*
{
  extern int optimize;
  if (optimize && REG_P (operands[0]) && REG_P (operands[1])
      && REGNO (operands[0]) == REGNO (operands[1])
      && already_sign_extended (insn, HImode, operands[0]))
    {
      cc_status = cc_prev_status;
      return \"\";
    }
  return \"cvthw %1,%0\";
}")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "general_operand" "=r,m")
	(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm,r")))]
  ""
  "*
{
  extern int optimize;
  if (optimize && REG_P (operands[0]) && REG_P (operands[1])
      && REGNO (operands[0]) == REGNO (operands[1])
      && already_sign_extended (insn, QImode, operands[0]))
    {
      cc_status = cc_prev_status;
      return \"\";
    }
  return \"cvtbw %1,%0\";
}")

; Pyramid doesn't have insns *called* "cvtbh" or "movzbh".
; But we can cvtbw/movzbw into a register, where there is no distinction
; between words and halfwords.

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
  ""
  "cvtbw %1,%0")

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
  ""
  "*
{
  cc_status.flags = CC_NOT_NEGATIVE;