i386.md

这是完整的gcc源代码

;  ""
;  "mul%B0 %2,%0")

(define_insn "umulhi3"
  [(set (match_operand:HI 0 "general_operand" "=a")
	(umult:SI (match_operand:HI 1 "general_operand" "%0")
		  (match_operand:HI 2 "general_operand" "rm")))
   (clobber (reg:HI 1))]
  ""
  "mul%W0 %2,%0")

(define_insn "umulsi3"
  [(set (match_operand:SI 0 "general_operand" "=a")
	(umult:SI (match_operand:SI 1 "general_operand" "%0")
		  (match_operand:SI 2 "general_operand" "rm")))
   (clobber (reg:SI 1))]
  ""
  "mul%L0 %2,%0")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "general_operand" "=f,m,f")
	(mult:DF (match_operand:DF 1 "general_operand" "%0,0,0")
		 (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
  "TARGET_80387"
   "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "general_operand" "=f,m,f")
	(mult:SF (match_operand:SF 1 "general_operand" "%0,0,0")
		 (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
  "TARGET_80387"
  "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
")

;;- divide instructions
(define_insn "divdf3"
  [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
	(div:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
		(match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
  "TARGET_80387"
  "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
	(div:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
		(match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
  "TARGET_80387"
  "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
")

;; Divide and Remainder instructions.

;; Copy operands 1 and 2 to new registers, so that there's no 
;; danger that put_var_into_stack will mess up the sharing match_dup needs.
;; CSE will get rid of the extra pseudo regs.
;; No problem if not optimizing, since then only `register' vars
;; will get pseudo regs, and they aren't allowed to have address taken.

(define_expand "divmodsi4"
  [(parallel [(set (match_operand:SI 0 "general_operand" "=a")
		   (div:SI (match_operand:SI 1 "general_operand" "0")
			   (match_operand:SI 2 "general_operand" "rm")))
	      (set (match_operand:SI 3 "general_operand" "=&d")
		   (mod:SI (match_dup 1) (match_dup 2)))])]
  ""
  "
{
  extern int optimize;
  if (optimize)
    {
      if (GET_CODE (operands[1]) == REG && REG_USERVAR_P (operands[1]))
	operands[1] = copy_to_mode_reg (SImode, operands[1]);
      if (GET_CODE (operands[2]) == REG && REG_USERVAR_P (operands[2]))
	operands[2] = copy_to_mode_reg (SImode, operands[2]);
    }
}")

(define_expand "udivmodsi4"
  [(parallel [(set (match_operand:SI 0 "general_operand" "=a")
		   (udiv:SI (match_operand:SI 1 "general_operand" "0")
			    (match_operand:SI 2 "general_operand" "rm")))
	      (set (match_operand:SI 3 "general_operand" "=&d")
		   (umod:SI (match_dup 1) (match_dup 2)))])]
  ""
  "
{
  extern int optimize;
  if (optimize)
    {
      if (GET_CODE (operands[1]) == REG && REG_USERVAR_P (operands[1]))
	operands[1] = copy_to_mode_reg (SImode, operands[1]);
      if (GET_CODE (operands[2]) == REG && REG_USERVAR_P (operands[2]))
	operands[2] = copy_to_mode_reg (SImode, operands[2]);
    }
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=a")
	(div:SI (match_operand:SI 1 "general_operand" "0")
		(match_operand:SI 2 "general_operand" "rm")))
   (set (match_operand:SI 3 "general_operand" "=&d")
	(mod:SI (match_dup 1) (match_dup 2)))]
  ""
  "cltd\;idiv%L0 %2")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=a")
	(udiv:SI (match_operand:SI 1 "general_operand" "0")
		(match_operand:SI 2 "general_operand" "rm")))
   (set (match_operand:SI 3 "general_operand" "=&d")
	(umod:SI (match_dup 1) (match_dup 2)))]
  ""
  "xor%L0 %3,%3\;div%L0 %2")

/*
;;this should be a valid double division which we may want to add

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=a")
	(udiv:DI (match_operand:DI 1 "general_operand" "a")
		(match_operand:SI 2 "general_operand" "rm")))
   (set (match_operand:SI 3 "general_operand" "=d")
	(umod:SI (match_dup 1) (match_dup 2)))]
  ""
  "div%L0 %2,%0")
*/

;;- and instructions

;; The `r' in `rm' for operand 3 looks redundant, but it causes
;; optional reloads to be generated if op 3 is a pseudo in a stack slot.

(define_insn "andsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm,r")
	(and:SI (match_operand:SI 1 "general_operand" "%0,0")
		(match_operand:SI 2 "general_operand" "ri,rm")))]
  ""
  "and%L0 %2,%0")

(define_insn "andhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm,r")
	(and:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "ri,rm")))]
  ""
  "and%W0 %2,%0")

(define_insn "andqi3"
  [(set (match_operand:QI 0 "general_operand" "=m,q")
	(and:QI (match_operand:QI 1 "general_operand" "%0,0")
		(match_operand:QI 2 "general_operand" "qn,qmn")))]
  ""
  "and%B0 %2,%0")

/* I am nervous about these two.. add them later..
;I presume this means that we have something in say op0= eax which is small
;and we want to and it with memory so we can do this by just an
;andb m,%al  and have success.
(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=r")
	(and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rm"))
		(match_operand:SI 2 "general_operand" "0")))]
  "GET_CODE (operands[2]) == CONST_INT
   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
  "and%W0 %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=q")
	(and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "qm"))
		(match_operand:SI 2 "general_operand" "0")))]
  "GET_CODE (operands[2]) == CONST_INT
   && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
  "and%L0 %1,%0")

*/



;;- Bit set (inclusive or) instructions

(define_insn "iorsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm,r")
	(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
		(match_operand:SI 2 "general_operand" "ri,rm")))]
  ""
  "or%L0 %2,%0")

(define_insn "iorhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm,r")
	(ior:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "ri,rm")))]
  ""
  "or%W0 %2,%0")

(define_insn "iorqi3"
  [(set (match_operand:QI 0 "general_operand" "=m,q")
	(ior:QI (match_operand:QI 1 "general_operand" "%0,0")
		(match_operand:QI 2 "general_operand" "qn,qmn")))]
  ""
  "or%B0 %2,%0")

;;- xor instructions

(define_insn "xorsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm,r")
	(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
		(match_operand:SI 2 "general_operand" "ri,rm")))]
  ""
  "xor%L0 %2,%0")

(define_insn "xorhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm,r")
	(xor:HI (match_operand:HI 1 "general_operand" "%0,0")
		(match_operand:HI 2 "general_operand" "ri,rm")))]
  ""
  "xor%W0 %2,%0")

(define_insn "xorqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(xor:QI (match_operand:QI 1 "general_operand" "%0")
		(match_operand:QI 2 "general_operand" "qn")))]
  ""
  "xor%B0 %2,%0")

;;- negation instructions
(define_insn "negsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(neg:SI (match_operand:SI 1 "general_operand" "0")))]
  ""
  "neg%L0 %0")

(define_insn "neghi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(neg:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "neg%W0 %0")

(define_insn "negqi2"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(neg:QI (match_operand:QI 1 "general_operand" "0")))]
  ""
  "neg%B0 %0")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "general_operand" "=f,!m")
	(neg:SF (match_operand:SF 1 "general_operand" "0,0")))]
  "TARGET_80387"
  "*FP_CALL1 (\"fchs\")")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "general_operand" "=f,!m")
	(neg:DF (match_operand:DF 1 "general_operand" "0,0")))]
  "TARGET_80387"
  "*FP_CALL1 (\"fchs\")")

;; Absolute value instructions

(define_insn "abssf2"
  [(set (match_operand:SF 0 "general_operand" "=f,!m")
	(abs:SF (match_operand:SF 1 "general_operand" "0,0")))]
  "TARGET_80387"
  "*FP_CALL1 (\"fabs\")")

(define_insn "absdf2"
  [(set (match_operand:DF 0 "general_operand" "=f,!m")
	(abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
  "TARGET_80387"
  "*FP_CALL1 (\"fabs\")")

;;- one complement instructions
(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(not:SI (match_operand:SI 1 "general_operand" "0")))]
  ""
  "not%L0 %0")

(define_insn "one_cmplhi2"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(not:HI (match_operand:HI 1 "general_operand" "0")))]
  ""
  "not%W0 %0")

(define_insn "one_cmplqi2"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(not:QI (match_operand:QI 1 "general_operand" "0")))]
  ""
  "not%B0 %0")

;;- arithmetic shift instructions

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(ashift:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sal%L0,%R0cl,%0);
  else if (REG_P (operands[1]) && GET_CODE (operands[2]) == CONST_INT
	   && INTVAL (operands[2]) == 1)
    return AS2 (add%L0,%1,%1);
  return AS2 (sal%L0,%2,%1);
}")

(define_insn "ashlhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(ashift:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:HI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sal%W0,%R0cl,%0);
  else
    return AS2 (sal%W0,%2,%1);
}")

(define_insn "ashlqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(ashift:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:QI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sal%B0,%R0cl,%0);
  else
    return AS2 (sal%B0,%2,%1);
}")

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sar%L0,%R0cl,%0);
  else
    return AS2 (sar%L0,%2,%0);
}")

(define_insn "ashrhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sar%W0,%R0cl,%0);
  else
    return AS2 (sar%W0,%2,%0);
}")

(define_insn "ashrqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (sar%B0,%R0cl,%0);
  return
    AS2 (sar%B0,%2,%1);
}")

;;- logical shift instructions

(define_insn "lshlsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(lshift:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shl%L0,%R0cl,%0);
  else
    return AS2 (shl%L0,%2,%1);
}")

(define_insn "lshlhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(lshift:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:HI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shl%W0,%R0cl,%0);
  else
    return AS2 (shl%W0,%2,%1);
}")

(define_insn "lshlqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(lshift:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:QI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shl%B0,%R0cl,%0);
  else
    return AS2 (shl%B0,%2,%1);
}")

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shr%L0,%R0cl,%0);
  else
    return AS2 (shr%L0,%2,%1);
}")

(define_insn "lshrhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shr%W0,%%cl,%0);
  else
    return AS2 (shr%W0,%2,%1);
}")

(define_insn "lshrqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
		     (match_operand:QI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (shr%B0,%%cl,%0);
  else
    return AS2 (shr%B0,%2,%1);
}")

;;- rotate instructions

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(rotate:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (rol%L0,%%cl,%0);
  else
    return AS2 (rol%L0,%2,%1);
}")

(define_insn "rotlhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(rotate:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:HI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (rol%W0,%%cl,%0);
  else
    return AS2 (rol%W0,%2,%1);
}")

(define_insn "rotlqi3"
  [(set (match_operand:QI 0 "general_operand" "=qm")
	(rotate:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:QI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (rol%B0,%%cl,%0);
  else
    return AS2 (rol%B0,%2,%1);
}")

(define_insn "rotrsi3"
  [(set (match_operand:SI 0 "general_operand" "=rm")
	(rotatert:SI (match_operand:SI 1 "general_operand" "0")
		     (match_operand:SI 2 "general_operand" "cI")))]
  ""
  "*
{
  if (REG_P (operands[2]))
    return AS2 (ror%L0,%%cl,%0);
  else
    return AS2 (ror%L0,%2,%1);
}")

(define_insn "rotrhi3"
  [(set (match_operand:HI 0 "general_operand" "=rm")
	(rotatert:HI (match_operand:HI 1 "general_operand" "0")
		     (match_operand:HI 2 "general_operand" "cI")))]