mips.md

这是完整的gcc源代码

  else if (code0 == MEM && code1 == CONST_INT && INTVAL (operands[1]) == 0)
    return \"sb\\t$0,%0\";

  else if (code0 == REG && CONSTANT_P (operands[1]))
    return \"la\\t%0,%a1\";

  else if (code0 == REG && code1 == PLUS
	   && GET_CODE (XEXP (operands[1], 0)) == REG
	   && GET_CODE (XEXP (operands[1], 1)) == CONST_INT)
    {
      operands[2] = XEXP (operands[1], 0);
      operands[3] = XEXP (operands[1], 1);
      return \"add%:\\t%0,%2,%3\";
    }

  abort_with_insn (insn, \"Bad movqi\");
  return 0;
}")

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=f,f,m,fy,*f,*y,*y,*m")
	(match_operand:SF 1 "general_operand" "f,m,f,F,*y,*f,*m,*y"))]
  ""
  "*
{
  enum rtx_code code0 = GET_CODE (operands[0]);
  enum rtx_code code1 = GET_CODE (operands[1]);

  if (code0 == REG)
    {
      if (code1 == REG)
	{
	  if (FP_REG_P (REGNO (operands[0])))
	    {
	      if (FP_REG_P (REGNO (operands[1])))
		return \"mov.s\\t%0,%1\";
	      else
		return \"mtc1\\t%1,%0\\t\\t# Calling sequence trick\";
	    }

	  else if (FP_REG_P (REGNO (operands[1])))
	    return \"mfc1\\t%0,%1\\t\\t# Calling sequence trick\";

	  else
	    return \"move\\t%0,%1\";
	}

      else if (code1 == CONST_DOUBLE)
	return \"li.s\\t%0,%1\";

      else if (code1 == MEM)
	return (GP_REG_P (REGNO (operands[0]))) ? \"lw\\t%0,%1\" : \"l.s\\t%0,%1\";
    }

  else if (code0 == MEM && code1 == REG)
    return (GP_REG_P (REGNO (operands[1]))) ? \"sw\\t%1,%0\" : \"s.s\\t%1,%0\";

  abort_with_insn (insn, \"Bad movsf\");
  return \"\";
}")


(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=f,f,m,fy,*f,*y,&*y,*m")
	(match_operand:DF 1 "general_operand" "f,m,f,F,*y,*f,*m,*y"))]
  ""
  "*
{
  extern rtx adj_offsettable_operand ();
  extern int offsettable_address_p ();

  enum rtx_code code0 = GET_CODE (operands[0]);
  enum rtx_code code1 = GET_CODE (operands[1]);

  if (code0 == REG)
    {
      if (code1 == REG)
	{
	  if (FP_REG_P (REGNO (operands[0])))
	    {
	      if (FP_REG_P (REGNO (operands[1])))
		return \"mov.d\\t%0,%1\";
	      else
		return \"mtc1\\t%L1,%0\\t\\t# Calling sequence trick\;mtc1\\t%M1,%D0\";
	    }

	  else if (FP_REG_P (REGNO (operands[1])))
	    return \"mfc1\\t%L0,%1\\t\\t# Calling sequence trick\;mfc1\\t%M0,%D1\";

	  else if (REGNO (operands[0]) != (REGNO (operands[1])+1))
	    return \"move\\t%0,%1\\n\\tmove\\t%D0,%D1\";

	  else
	    return \"move\\t%D0,%D1\\n\\tmove\\t%0,%1\";
	}

      else if (code1 == CONST_DOUBLE)
	return \"li.d\\t%0,%1\";

      else if (code1 == MEM)
	{
	  if (FP_REG_P (REGNO (operands[0])))
	    return \"l.d\\t%0,%1\";

	  else if (offsettable_address_p (1, DFmode, XEXP (operands[1], 0)))
	    {
	      operands[2] = adj_offsettable_operand (operands[1], 4);
	      if (reg_mentioned_p (operands[0], operands[1]))
		return \"lw\\t%D0,%2\;lw\\t%0,%1\";
	      else
		return \"lw\\t%0,%1\;lw\\t%D0,%2\";
	    }

	  else
	    {
	      operands[2] = gen_rtx (REG, Pmode, 1);
	      return \".set\\tnoat\;la\\t%2,%1\;lw\\t%0,0(%2)\;lw\\t%D0,4(%2)\;set\\tat\";
	    }
	}
    }

  else if (code0 == MEM && code1 == REG)
    {
      if (FP_REG_P (REGNO (operands[1])))
	return \"s.d\\t%1,%0\";

      else if (offsettable_address_p (1, DFmode, XEXP (operands[0], 0)))
	{
	  operands[2] = adj_offsettable_operand (operands[0], 4);
	  return \"sw\\t%1,%0\;sw\\t%D1,%2\";
	}

      else
	{
	  operands[2] = gen_rtx (REG, Pmode, 1);
	  return \".set\\tnoat\;la\\t%2,%0\;sw\\t%1,0(%2)\;sw\\t%D1,4(%2)\;set\\tat\";
	}
    }

  abort_with_insn (insn, \"Bad movdf\");
  return \"\";
}")


;;
;;  ....................
;;
;;          OTHER ARITHMETIC AND SHIFT
;;
;;  ....................

(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "r")
		   (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);

  return \"sll\\t%0,%1,%2\";
}")

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);

  return \"sra\\t%0,%1,%2\";
}")

(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);

  return \"srl\\t%0,%1,%2\";
}")

(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "sub%:\\t%0,$0,%1")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=f")
	(neg:DF (match_operand:DF 1 "register_operand" "f")))]
  ""
  "neg.d\\t%0,%1")

(define_insn "negsf2"

  [(set (match_operand:SF 0 "register_operand" "=f")
	(neg:SF (match_operand:SF 1 "register_operand" "f")))]
  ""
  "neg.s\\t%0,%1")


(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "nor\\t%0,$0,%1")

;;
;;  ....................
;;
;;          COMPARISONS
;;
;;  ....................

					;;- Order is significant here
					;;- because there are untyped
					;;- comparisons generated by
					;;- the optimizer
                                        ;;- (set (cc0)
                                        ;;-      (compare (const_int 2)
                                        ;;-           (const_int 1)))

(define_insn "cmpsi"
  [(set (cc0)
	(compare (match_operand:SI 0 "register_operand" "r")
		 (match_operand:SI 1 "arith_operand" "rI")))]
  ""
  "*
    compare_collect (SImode, operands[0], operands[1]);
    return \"\\t\\t\\t\\t# cmpsi\\t%0,%1\";
")


(define_insn ""
  [(set (cc0)
	(match_operand:SI 0 "register_operand" "r"))]
  ""
  "*
    compare_collect (SImode, operands[0], gen_rtx (REG, SImode, 0));
    return \"\\t\\t\\t\\t# (set (cc0)\\t%0)\";
")

;; These patterns are hopelessly invalid, because
;; comparing subword values properly requires extending them.

;; (define_insn "cmphi"
;;   [(set (cc0)
;; 	(compare (match_operand:HI 0 "register_operand" "r")
;; 		 (match_operand:HI 1 "register_operand" "r")))]
;;   ""
;;   "*
;;     compare_collect (HImode, operands[0], operands[1]);
;;     return      \" #\\tcmphi\\t%0,%1\";
;;   ")
;; 
;; (define_insn "cmpqi"
;;   [(set (cc0)
;; 	(compare (match_operand:QI 0 "register_operand" "r")
;; 		 (match_operand:QI 1 "register_operand" "r")))]
;;   ""
;;   "*
;;     compare_collect (QImode, operands[0], operands[1]);
;;     return      \" #\\tcmpqi\\t%0,%1\";
;;   ")
;; 
;; (define_insn ""
;;   [(set (cc0)
;; 	(match_operand:QI 0 "register_operand" "r"))]
;;   ""
;;   "*
;;     compare_collect (QImode, operands[0], gen_rtx (REG, QImode, 0));
;;     return \" #\\t (set (cc0)\\t%0)\";
;; ")
;; 
;; (define_insn ""
;;   [(set (cc0)
;; 	(match_operand:HI 0 "register_operand" "r"))]
;;   ""
;;   "*
;;     compare_collect (HImode, operands[0], gen_rtx (REG, HImode, 0));
;;     return \" #\\t (set (cc0)\\t%0)\";
;; ")

(define_insn "cmpdf"
  [(set (cc0)
	(compare (match_operand:DF 0 "register_operand" "f")
		 (match_operand:DF 1 "register_operand" "f")))]
  ""
  "*
    compare_collect (DFmode, operands[0], operands[1]);
    return \" #\\t\\t\\t\\tcmpdf\\t%0,%1\" ;
")

(define_insn "cmpsf"
  [(set (cc0)
	(compare (match_operand:SF 0 "register_operand" "f")
		 (match_operand:SF 1 "register_operand" "f")))]
  ""
  "*
    compare_collect (SFmode, operands[0], operands[1]);
    return \"\\t\\t\\t\\t# cmpsf\\t%0,%1\" ;
")

;;
;;  ....................
;;
;;          BRANCHES
;;
;;  ....................

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == REG)
    return \"j\\t%0\";
  else
    return \"j\\t%l0\";
}")


(define_insn "tablejump"
  [(set (pc)
	(match_operand:SI 0 "register_operand" "r"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "j\\t%0")


(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.eq.d\\t%0,%1\\t\\t# beq\", br_ops);
      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.eq.s\\t%0,%1\\t\\t# beq\", br_ops);
      output_asm_insn (\"bc1t\\t%2\\t\\t# beq\", br_ops);
    }
  else
    {
      output_asm_insn (\"beq\\t%0,%1,%2\\t\\t# beq\", br_ops);
    }
  return \"\";
}
   ")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.eq.d\\t%0,%1\\t\\t# bne\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bne\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.eq.s\\t%0,%1\\t\\t# bne\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bne\", br_ops);
    }
  else
    {
      output_asm_insn (\"bne\\t%0,%1,%2\\t\\t# bne\", br_ops);
    }
  return \"\";
}

")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# bgt branch %0 > %1\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bgt\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# bgt branch %0 > %1\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bgt\", br_ops);
    }
  else
    {
      output_asm_insn (\"bgt\\t%0,%1,%2\\t\\t# bgt\", br_ops);
    }
  return \"\";
}

")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# blt\", br_ops);
      output_asm_insn (\"bc1t\\t%2\\t\\t# blt\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# blt\", br_ops);
      output_asm_insn (\"bc1t\\t%2\\t\\t# blt\", br_ops);
    }
  else
    {
      output_asm_insn (\"blt\\t%0,%1,%2\\t\\t# blt\", br_ops);
    }
  return \" #\\tblt\\t%l0\\t\\t# blt\";
}
")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.le.d\\t%0,%1\\t\\t# bgtu\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bgtu\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.le.s\\t%0,%1\\t\\t# bgtu\", br_ops);
      output_asm_insn (\"bc1f\\t%2\\t\\t# bgtu\", br_ops);
    }
  else
    {
      output_asm_insn (\"bgtu\\t%0,%1,%2\\t\\t# bgtu\", br_ops);
    }
  return \" #\\tbgtu\\t%l0\\t\\t# bgtu\";
}
")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{
  rtx br_ops[3];
  enum machine_mode mode;
  compare_restore (br_ops,  &mode, insn);
  br_ops[2] = operands[0];
  if (mode == DFmode)
    {
      output_asm_insn (\"c.lt.d\\t%0,%1\\t\\t# bltu\", br_ops);
      output_asm_insn (\"bc1t\\t%2\\t\\t# bltu\", br_ops);
    }
  else if  (mode == SFmode)
    {
      output_asm_insn (\"c.lt.s\\t%0,%1\\t\\t# bltu\", br_ops);