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  [(set (pc)	(if_then_else	 (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))]  ""  "jbc %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (ne (sign_extract:SI (match_operand:QI 0 "general_operand" "g")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  ""  "jbc %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (eq (sign_extract:SI (match_operand:QI 0 "general_operand" "g")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  ""  "jbs %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))]  "GET_CODE (operands[0]) != MEM   || ! mode_dependent_address_p (XEXP (operands[0], 0))"  "jbs %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))]  "GET_CODE (operands[0]) != MEM   || ! mode_dependent_address_p (XEXP (operands[0], 0))"  "jbc %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (eq (and:SI (match_operand:SI 0 "general_operand" "g")		     (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  "GET_CODE (operands[1]) == CONST_INT   && exact_log2 (INTVAL (operands[1])) >= 0   && (GET_CODE (operands[0]) != MEM       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"  "*{  operands[1]    = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));  return \"jbs %1,%0,%l2\";}")(define_insn ""  [(set (pc)	(if_then_else	 (eq (and:SI (match_operand:SI 0 "general_operand" "g")		     (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))]  "GET_CODE (operands[1]) == CONST_INT   && exact_log2 (INTVAL (operands[1])) >= 0   && (GET_CODE (operands[0]) != MEM       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"  "*{  operands[1]    = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));  return \"jbc %1,%0,%l2\";}")(define_insn ""  [(set (pc)	(if_then_else	 (ne (and:SI (match_operand:SI 0 "general_operand" "g")		     (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  "GET_CODE (operands[1]) == CONST_INT   && exact_log2 (INTVAL (operands[1])) >= 0   && (GET_CODE (operands[0]) != MEM       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"  "*{  operands[1]    = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));  return \"jbc %1,%0,%l2\";}")(define_insn ""  [(set (pc)	(if_then_else	 (ne (and:SI (match_operand:SI 0 "general_operand" "g")		     (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))]  "GET_CODE (operands[1]) == CONST_INT   && exact_log2 (INTVAL (operands[1])) >= 0   && (GET_CODE (operands[0]) != MEM       || ! mode_dependent_address_p (XEXP (operands[0], 0)))"  "*{  operands[1]    = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));  return \"jbs %1,%0,%l2\";}")(define_insn ""  [(set (pc)	(if_then_else	 (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  "GET_CODE (operands[0]) != MEM   || ! mode_dependent_address_p (XEXP (operands[0], 0))"  "jbc %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")			      (const_int 1)			      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))]  "GET_CODE (operands[0]) != MEM   || ! mode_dependent_address_p (XEXP (operands[0], 0))"  "jbs %1,%0,%l2");; Subtract-and-jump and Add-and-jump insns.;; These are not used when output is for the Unix assembler;; because it does not know how to modify them to reach far.;; Normal sob insns.(define_insn ""  [(set (pc)	(if_then_else	 (gt (plus:SI (match_operand:SI 0 "general_operand" "+g")		      (const_int -1))	     (const_int 0))	 (label_ref (match_operand 1 "" ""))	 (pc)))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int -1)))]  "!TARGET_UNIX_ASM"  "jsobgtr %0,%l1")(define_insn ""  [(set (pc)	(if_then_else	 (ge (plus:SI (match_operand:SI 0 "general_operand" "+g")		      (const_int -1))	     (const_int 0))	 (label_ref (match_operand 1 "" ""))	 (pc)))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int -1)))]  "!TARGET_UNIX_ASM"  "jsobgeq %0,%l1");; Reversed sob insns.(define_insn ""  [(set (pc)	(if_then_else	 (le (plus:SI (match_operand:SI 0 "general_operand" "+g")		      (const_int -1))	     (const_int 0))	 (pc)	 (label_ref (match_operand 1 "" ""))))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int -1)))]  "!TARGET_UNIX_ASM"  "jsobgtr %0,%l1")(define_insn ""  [(set (pc)	(if_then_else	 (lt (plus:SI (match_operand:SI 0 "general_operand" "+g")		      (const_int -1))	     (const_int 0))	 (pc)	 (label_ref (match_operand 1 "" ""))))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int -1)))]  "!TARGET_UNIX_ASM"  "jsobgeq %0,%l1");; Normal aob insns.(define_insn ""  [(set (pc)	(if_then_else	 (lt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")			       (const_int 1))		      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int 1)))]  "!TARGET_UNIX_ASM"  "jaoblss %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (le (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")			       (const_int 1))		      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (label_ref (match_operand 2 "" ""))	 (pc)))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int 1)))]  "!TARGET_UNIX_ASM"  "jaobleq %1,%0,%l2");; Reverse aob insns.(define_insn ""  [(set (pc)	(if_then_else	 (ge (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")			       (const_int 1))		      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int 1)))]  "!TARGET_UNIX_ASM"  "jaoblss %1,%0,%l2")(define_insn ""  [(set (pc)	(if_then_else	 (gt (compare (plus:SI (match_operand:SI 0 "general_operand" "+g")			       (const_int 1))		      (match_operand:SI 1 "general_operand" "g"))	     (const_int 0))	 (pc)	 (label_ref (match_operand 2 "" ""))))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int 1)))]  "!TARGET_UNIX_ASM"  "jaobleq %1,%0,%l2");; Something like a sob insn, but compares against -1.;; This finds `while (foo--)' which was changed to `while (--foo != -1)'.(define_insn ""  [(set (pc)	(if_then_else	 (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "g")			       (const_int -1))		      (const_int -1))	     (const_int 0))	 (label_ref (match_operand 1 "" ""))	 (pc)))   (set (match_dup 0)	(plus:SI (match_dup 0)		 (const_int -1)))]  ""  "decl %0\;jgequ %l1");; Note that operand 1 is total size of args, in bytes,;; and what the call insn wants is the number of words.(define_insn "call"  [(call (match_operand:QI 0 "general_operand" "g")	 (match_operand:QI 1 "general_operand" "g"))]  ""  "*  if (INTVAL (operands[1]) > 255 * 4)    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */    return \"calls $0,%0\;addl2 %1,sp\";  operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);  return \"calls %1,%0\";")(define_insn "call_value"  [(set (match_operand 0 "" "=g")	(call (match_operand:QI 1 "general_operand" "g")	      (match_operand:QI 2 "general_operand" "g")))]  ""  "*  if (INTVAL (operands[2]) > 255 * 4)    /* Vax `calls' really uses only one byte of #args, so pop explicitly.  */    return \"calls $0,%1\;addl2 %2,sp\";  operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3)/ 4);  return \"calls %2,%1\";")(define_insn "return"  [(return)]  ""  "ret")(define_insn "nop"  [(const_int 0)]  ""  "nop")(define_insn "casesi"  [(set (pc)	(if_then_else (le (minus:SI (match_operand:SI 0 "general_operand" "g")				    (match_operand:SI 1 "general_operand" "g"))			  (match_operand:SI 2 "general_operand" "g"))		      (plus:SI (sign_extend:SI				(mem:HI (plus:SI (pc)						 (minus:SI (match_dup 0)							   (match_dup 1)))))			       (label_ref:SI (match_operand 3 "" "")))		      (pc)))]  ""  "casel %0,%1,%2");; This used to arise from the preceding by simplification;; if operand 1 is zero.  Perhaps it is no longer necessary.(define_insn ""  [(set (pc)	(if_then_else (le (match_operand:SI 0 "general_operand" "g")			  (match_operand:SI 1 "general_operand" "g"))		      (plus:SI (sign_extend:SI				(mem:HI (plus:SI (pc)						 (minus:SI (match_dup 0)							   (const_int 0)))))			       (label_ref:SI (match_operand 3 "" "")))		      (pc)))]  ""  "casel %0,$0,%1");; This arises from the preceding by simplification if operand 1 is zero.(define_insn ""  [(set (pc)	(if_then_else (le (match_operand:SI 0 "general_operand" "g")			  (match_operand:SI 1 "general_operand" "g"))		      (plus:SI (sign_extend:SI				(mem:HI (plus:SI (pc)						 (match_dup 0))))			       (label_ref:SI (match_operand 3 "" "")))		      (pc)))]  ""  "casel %0,$0,%1");; This arises from casesi if operand 0 is a constant, in range.(define_insn ""  [(set (pc)	(plus:SI (sign_extend:SI		  (mem:HI (plus:SI (pc)				   (match_operand:SI 0 "general_operand" "g"))))		 (label_ref:SI (match_operand 3 "" ""))))]  ""  "casel %0,$0,%0");; This arises from the above if both operands are the same.(define_insn ""  [(set (pc)        (plus:SI (sign_extend:SI (mem:HI (pc)))		 (label_ref:SI (match_operand 3 "" ""))))]  ""  "casel $0,$0,$0");;- load or push effective address ;; These come after the move and add/sub patterns;; because we don't want pushl $1 turned into pushad 1.;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3.(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(match_operand:QI 1 "address_operand" "p"))]  ""  "*{  if (push_operand (operands[0], SImode))    return \"pushab %a1\";  return \"movab %a1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(match_operand:HI 1 "address_operand" "p"))]  ""  "*{  if (push_operand (operands[0], SImode))    return \"pushaw %a1\";  return \"movaw %a1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(match_operand:SI 1 "address_operand" "p"))]  ""  "*{  if (push_operand (operands[0], SImode))    return \"pushal %a1\";  return \"moval %a1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(match_operand:SF 1 "address_operand" "p"))]  ""  "*{  if (push_operand (operands[0], SImode))    return \"pushaf %a1\";  return \"movaf %a1,%0\";}")(define_insn ""  [(set (match_operand:SI 0 "general_operand" "=g")	(match_operand:DF 1 "address_operand" "p"))]  ""  "*{  if (push_operand (operands[0], SImode))    return \"pushad %a1\";  return \"movad %a1,%0\";}");; Optimize   extzv ...,z;    andl2 ...,z;; with other operands constant.(define_peephole  [(set (match_operand:SI 0 "general_operand" "g")	(zero_extract:SI (match_operand:SI 1 "general_operand" "g")			 (match_operand:SI 2 "general_operand" "g")			 (match_operand:SI 3 "general_operand" "g")))   (set (match_operand:SI 4 "general_operand" "g")	(and:SI (match_dup 0)		(match_operand:SI 5 "general_operand" "g")))]  "GET_CODE (operands[2]) == CONST_INT   && GET_CODE (operands[3]) == CONST_INT   && (INTVAL (operands[2]) + INTVAL (operands[3])) == 32   && GET_CODE (operands[5]) == CONST_INT   && dead_or_set_p (insn, operands[0])"  "*{  unsigned long mask = INTVAL (operands[5]);  operands[3] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[3]));  if ((floor_log2 (mask) + 1) >= INTVAL (operands[2]))    mask &= ((1 << INTVAL (operands[2])) - 1);  operands[5] = gen_rtx (CONST_INT, VOIDmode, ~mask);  if (push_operand (operands[4], SImode))    {      output_asm_insn (\"rotl %3,%1,%0\", operands);      return \"bicl3 %5,%0,%4\";    }  else    {      output_asm_insn (\"rotl %3,%1,%4\", operands);      return \"bicl2 %5,%4\";    }}");; Optimize   andl3 x,y,z; extzv z,....,z(define_peephole  [(set (match_operand:SI 0 "general_operand" "g")	(and:SI (match_operand:SI 1 "general_operand" "g")		(match_operand:SI 2 "general_operand" "g")))   (set (match_operand 3 "general_operand" "g")	(zero_extract:SI (match_dup 0)			 (match_operand:SI 4 "general_operand" "g")			 (match_operand:SI 5 "general_operand" "g")))]  "GET_CODE (operands[2]) == CONST_INT   && GET_CODE (operands[4]) == CONST_INT   && GET_CODE (operands[5]) == CONST_INT   && (INTVAL (operands[4]) + INTVAL (operands[5])) == 32   && dead_or_set_p (insn, operands[0])"  "*{  unsigned long mask = INTVAL (operands[2]);  mask &= ~((1 << INTVAL (operands[5])) - 1);  operands[2] = gen_rtx (CONST_INT, VOIDmode, ~mask);  operands[5] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[5]));  if (rtx_equal_p (operands[0], operands[1]))    output_asm_insn (\"bicl2 %2,%0\", operands);  else    output_asm_insn (\"bicl3 %2,%1,%0\", operands);  return \"rotl %5,%0,%3\";}");;- Local variables:;;- mode:emacs-lisp;;- comment-start: ";;- ";;- eval: (set-syntax-table (copy-sequence (syntax-table)));;- eval: (modify-syntax-entry ?[ "(]");;- eval: (modify-syntax-entry ?] ")[");;- eval: (modify-syntax-entry ?{ "(}");;- eval: (modify-syntax-entry ?} "){");;- End:

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