convex.md

这是完整的gcc源代码

  "
{
  if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 0)
    emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			gen_rtx (LSHIFT, DImode, operands[1], operands[2])));
  else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
    {
      int rshift = - INTVAL (operands[2]);
      operands[3] = force_reg
	(DImode,
	 immed_double_const (1 << (63 - rshift), 1 << (31 - rshift), DImode));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (LSHIFT, DImode, operands[1], operands[2])));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (XOR, DImode, operands[0], operands[3])));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (MINUS, DImode, operands[0], operands[3])));
    }
  else
    {
      operands[3] =
	force_reg (DImode, immed_double_const (0, 1 << 31, DImode));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (LSHIFT, DImode, operands[1], operands[2])));
      emit_insn (gen_rtx (SET, VOIDmode, operands[3],
			  gen_rtx (LSHIFT, DImode, operands[3], operands[2])));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (XOR, DImode, operands[0], operands[3])));
      emit_insn (gen_rtx (SET, VOIDmode, operands[0],
			  gen_rtx (MINUS, DImode, operands[0], operands[3])));
  }
  DONE;
}")

(define_expand "ashrdi3"
  [(match_operand:DI 0 "register_operand" "=d")
   (match_operand:DI 1 "register_operand" "0")
   (match_operand:SI 2 "nonmemory_operand" "di")]
  ""
  "
{
  emit_insn (gen_ashldi3 (operands[0], operands[1],
			  negate_rtx (SImode, operands[2])));
  DONE;	    
}")

(define_insn "lshldi3"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(lshift:DI (match_operand:DI 1 "register_operand" "0")
		   (match_operand:SI 2 "nonmemory_operand" "di")))]
  ""
  "shf %2,%0")

(define_expand "lshrdi3"
  [(set (match_operand:DI 0 "register_operand" "=d")
	(lshift:DI (match_operand:DI 1 "register_operand" "0")
		   (match_operand:SI 2 "nonmemory_operand" "di")))]
  ""
  "operands[2] = negate_rtx (SImode, operands[2]);")

;; __builtin instructions

(define_insn "sqrtdf2"
  [(set (match_operand:DF 0 "register_operand" "=d")
	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
  "TARGET_C2"
  "sqrt.d %0")

(define_insn "sqrtsf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
  "TARGET_C2"
  "sqrt.s %0")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=d")
	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
		  (const_int 1)))]
  ""
  "tzc %1,%0\;le.w #32,%0\;jbrs.f .+6\;ld.w #-1,%0")

(define_expand "ffssi2"
  [(set (match_operand:SI 0 "register_operand" "=d")
	(minus:SI (ffs:SI (match_operand:SI 1 "register_operand" "d"))
		  (const_int 1)))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (const_int 1)))]
  ""
  "")

(define_insn "abssf2"
  [(set (match_operand:SF 0 "register_operand" "=d")
	(abs:SF (match_operand:SF 1 "register_operand" "0")))]
  ""
  "and #0x7fffffff,%0")

(define_expand "absdf2"
  [(set (subreg:DI (match_operand:DF 0 "register_operand" "=d") 0)
	(and:DI (subreg:DI (match_operand:DF 1 "register_operand" "d") 0)
		(match_dup 2)))]
  ""
  "operands[2] = force_reg (DImode,
			    immed_double_const (-1, 0x7fffffff, DImode));")

(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "jbr %l0")

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"eq\", 't'); ")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"eq\", 'f'); ")

(define_insn "bgt"
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"le\", 'f'); ")

(define_insn "bgtu"
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"leu\", 'f'); ")

(define_insn "blt"
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"lt\", 't'); ")

(define_insn "bltu"
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"ltu\", 't'); ")

(define_insn "bge"
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"lt\", 'f'); ")

(define_insn "bgeu"
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"ltu\", 'f'); ")

(define_insn "ble"
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"le\", 't'); ")

(define_insn "bleu"
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "* return gen_cmp (operands[0], \"leu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"eq\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ne (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"eq\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"le\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (gtu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"leu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (lt (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"lt\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ltu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"ltu\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (ge (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"lt\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (geu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"ltu\", 't'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (le (cc0)
			  (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"le\", 'f'); ")

(define_insn ""
  [(set (pc)
	(if_then_else (leu (cc0)
			   (const_int 0))
		      (pc)
		      (label_ref (match_operand 0 "" ""))))]
  ""
  "* return gen_cmp (operands[0], \"leu\", 'f'); ")

;;  - Calls
;;
;; arg count word may be omitted to save a push and let gcc try to
;; combine the arg list pop.  RETURN_POPS_ARGS from tm.h decides this.

(define_insn "call"
  [(call (match_operand:QI 0 "general_operand" "g")
	 (match_operand:SI 1 "general_operand" "g"))]
  ""
  "*
{
  if (! RETURN_POPS_ARGS (ignoreme)) 
    {
      if (operands[1] == const0_rtx)
	return \"calls %0\";
      if (! reg_mentioned_p (arg_pointer_rtx, operands[0]))
	return \"mov sp,ap\;calls %0\;ld.w 12(fp),ap\";
      operands[0] = XEXP (operands[0], 0);
      return \"ld.w %0,a1\;mov sp,ap\;calls (a1)\;ld.w 12(fp),ap\";
    }
  operands[1] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[1]) + 3)/ 4);
  if (! reg_mentioned_p (arg_pointer_rtx, operands[0]))
    return \"mov sp,ap\;pshea %a1\;calls %0\;ld.w 12(fp),ap\;add.w #4*%a1+4,sp\";
  operands[0] = XEXP (operands[0], 0);
  return \"ld.w %0,a1\;mov sp,ap\;pshea %a1\;calls (a1)\;ld.w 12(fp),ap\;add.w #4*%a1+4,sp\";
}")

(define_insn "call_value"
  [(set (match_operand 0 "" "=g")
	(call (match_operand:QI 1 "general_operand" "g")
	      (match_operand:SI 2 "general_operand" "g")))]
  ""
  "*
{
  if (! RETURN_POPS_ARGS (ignoreme)) 
    {
      if (operands[2] == const0_rtx)
	return \"calls %1\";
      if (! reg_mentioned_p (arg_pointer_rtx, operands[1]))
	return \"mov sp,ap\;calls %1\;ld.w 12(fp),ap\";
      operands[1] = XEXP (operands[1], 0);
      return \"ld.w %1,a1\;mov sp,ap\;calls (a1)\;ld.w 12(fp),ap\";
    }
  operands[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) + 3) / 4);
  if (! reg_mentioned_p (arg_pointer_rtx, operands[1]))
    return \"mov sp,ap\;pshea %a2\;calls %1\;ld.w 12(fp),ap\;add.w #4*%a2+4,sp\";
  operands[1] = XEXP (operands[1], 0);
  return \"ld.w %1,a1\;mov sp,ap\;pshea %a2\;calls (a1)\;ld.w 12(fp),ap\;add.w #4*%a2+4,sp\";
}")

(define_insn "return"
  [(return)]
  ""
  "rtn")

(define_insn "nop"
  [(const_int 0)]
  ""
  "nop")

(define_insn "tablejump"
  [(set (pc) (match_operand:SI 0 "address_operand" "p"))
   (use (label_ref (match_operand 1 "" "")))]
  ""
  "jmp %a0")

;; - fix up the code generated for bit field tests

;; cc0 = (x >> k1) & k2  -->  cc0 = x & (k2 << k1)
;; cc0 = (x << k1) & k2  -->  cc0 = x & (k2 >> k1)  
;; provided k2 and (k2 << k1) don't include the sign bit

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "r")
	(lshift:SI (match_dup 0)
		   (match_operand 1 "immediate_operand" "i")))
   (set (match_dup 0)
	(and:SI (match_dup 0)
		(match_operand 2 "immediate_operand" "i")))
   (set (cc0) (match_dup 0))]
  "dead_or_set_p (insn, operands[0])
   && GET_CODE (operands[1]) == CONST_INT
   && GET_CODE (operands[2]) == CONST_INT
   && INTVAL (operands[2]) >= 0
   && (INTVAL (operands[2]) << INTVAL (operands[1])) >= 0"
  "*
{
  operands[2] = gen_rtx (CONST_INT, VOIDmode, 
			 INTVAL (operands[2]) >> INTVAL (operands[1]));
  output_asm_insn (\"and %2,%0\", operands);
  return set_cmp (operands[0], const0_rtx, 'w');
}")

;; same as above where x is (y & 0xff...) caused by a zero extend

(define_peephole
  [(set (match_operand:SI 0 "register_operand" "r")
	(zero_extend:SI (match_operand 1 "register_operand" "0")))
   (set (match_dup 0)
	(lshift:SI (match_dup 0)
		   (match_operand 2 "immediate_operand" "i")))
   (set (match_dup 0)
	(and:SI (match_dup 0)
		(match_operand 3 "immediate_operand" "i")))
   (set (cc0) (match_dup 0))]
  "dead_or_set_p (insn, operands[0])
   && REGNO (operands[0]) == REGNO (operands[1])
   && GET_CODE (operands[2]) == CONST_INT
   && GET_CODE (operands[3]) == CONST_INT
   && (INTVAL (operands[3]) << INTVAL (operands[2])) >= 0"
  "*
{
  operands[3] = gen_rtx (CONST_INT, VOIDmode, 
			 (INTVAL (operands[3]) >> INTVAL (operands[2])) &
			 ~((-1) << GET_MODE_BITSIZE (GET_MODE (operands[1]))));
  output_asm_insn (\"and %3,%0\", operands);
  return set_cmp (operands[0], const0_rtx, 'w');
}")

;;- Local variables:
;;- mode:emacs-lisp
;;- comment-start: ";;- "
;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
;;- eval: (modify-syntax-entry ?[ "(]")
;;- eval: (modify-syntax-entry ?] ")[")
;;- eval: (modify-syntax-entry ?{ "(}")
;;- eval: (modify-syntax-entry ?} "){")
;;- End: