m88k.md

这是完整的gcc源代码

}")

(define_insn "iorcbsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operand:SI 1 "register_operand" "%r")
		(not:SI (match_operand:SI 2 "register_operand" "r"))))]
  ""
  "or.c %0,%1,%2")

;;- xor instructions (with complement also)
(define_insn "xorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"xor %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"xor %0,%1,%2\";
  if ((i & 0xffff) == 0)
    return \"xor.u %0,%1,hi16(%2)\";
  return \"xor.u %0,%1,hi16(%2)\;xor %0,%1,lo16(%2)\";
}")

(define_insn "xorcbsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(xor:SI (match_operand:SI 1 "register_operand" "%r")
		(not:SI (match_operand:SI 2 "register_operand" "r"))))]
  ""
  "xor.c %0,%1,%2")

;;- one complement instructions
(define_insn "one_cmplsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(not:SI (match_operand:SI 1 "register_operand" "r")))]
  ""
  "xor.c %0,%1,r0")

;; Optimized special case of shifting.
;; Must precede the general case.

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
		     (const_int 24)))]
  ""
  "ld.b %0,%1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
		     (const_int 24)))]
  ""
  "ld.bu %0,%1")

;;- arithmetic shift instructions
(define_insn "ashlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashift:SI (match_operand:SI 1 "register_operand" "r")
		   (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"mak %0,%1,0<%2>\";
  return \"mask %0,%2,0x1f\;mak %0,%1,%0\";
}")

(define_insn "ashrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"ext %0,%1,0<%2>\";
  return \"mask %0,%2,0x1f\;ext %0,%1,%0\";
}")

;;- logical shift instructions
(define_insn "lshrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"extu %0,%1,0<%2>\";
  return \"mask %0,%2,0x1f\;extu %0,%1,%0\";
}")

;;- rotate instructions

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(rotate:SI (match_operand:SI 1 "register_operand" "r")
		   (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      operands[2] = gen_rtx (CONST_INT, SImode, 32 - INTVAL (operands[2]));
      return \"rot %0,%1,%2\";
    }
  return \"or %0,r0,32\;sub %0,%2,%0\;rot %0,%1,%0\";
}")

(define_insn "rotrsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
		     (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "rot %0,%1,%2")

;; Special cases of bit-field insns which we should
;; recognize in preference to the general case.
;; These handle aligned 8-bit and 16-bit fields,
;; which can usually be done with move instructions.

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
			 (match_operand:SI 1 "int5_operand" "K")
			 (match_operand:SI 2 "int5_operand" "K"))
	(match_operand:SI 3 "register_operand" "r"))]
  "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
   && INTVAL (operands[2]) % INTVAL (operands[1]) == 0"
  "*
{
  if (REG_P (operands[0]))
    {
      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
        return \"mak %0,%3,%1<%2>\";
    }
  else
    operands[0]
      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);

  if (GET_CODE (operands[3]) == MEM)
    operands[3] = adj_offsettable_operand (operands[3],
					   (32 - INTVAL (operands[1])) / 8);
  if (INTVAL (operands[1]) == 8)
    return \"st.b %3,%0\";
  return \"st.w %3,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=&r")
	(zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
			 (match_operand:SI 2 "int5_operand" "K")
			 (match_operand:SI 3 "int5_operand" "K")))]
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
  "*
{
  if (REG_P (operands[1]))
    {
      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
	return \"extu %0,%1,%2<%3>\";
    }
  else
    operands[1]
      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);

  if (GET_CODE (operands[0]) == MEM)
    operands[0] = adj_offsettable_operand (operands[0],
					   (32 - INTVAL (operands[1])) / 8);
  if (INTVAL (operands[2]) == 8)
    return \"ld.bu %0,%1\";
  return \"ld.hu %0,%1\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
			 (match_operand:SI 2 "int5_operand" "K")
			 (match_operand:SI 3 "int5_operand" "K")))]
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
   && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
  "*
{
  if (REG_P (operands[1]))
    {
      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
	return \"extu %0,%1,%2<%3>\";
    }
  else
    operands[1]
      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);

  if (INTVAL (operands[2]) == 8)
    return \"ld.b %0,%1\";
  return \"ld.h %0,%1\";
}")

;; Bit field instructions.

(define_insn "extv"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extract:SI (match_operand:QI 1 "register_operand" "r,r")
			 (match_operand:SI 2 "arith_operand" "K,rK")
			 (match_operand:SI 3 "arith_operand" "K,&r")))]
  ""
  "*
{
  if (GET_CODE (operands[3]) == CONST_INT)
    return \"ext %0,%1,%2<%3>\";
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[2]) & 0x1f) << 5);
      return \"mask %3,%3,0x1f\;or %3,%3,%2\;ext %0,%1,%3\";
    }
  return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(sign_extract:SI (match_operand:SI 1 "register_operand" "r,r")
			 (match_operand:SI 2 "arith_operand" "K,rK")
			 (match_operand:SI 3 "arith_operand" "K,&r")))]
  ""
  "*
{
  if (GET_CODE (operands[3]) == CONST_INT)
    return \"ext %0,%1,%2<%3>\";
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[2]) & 0x1f) << 5);
      return \"mask %3,%3,0x1f\;or %3,%3,%2\;ext %0,%1,%3\";
    }
  return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
}")

(define_insn "extzv"
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extract:SI (match_operand:QI 1 "register_operand" "r,r")
			 (match_operand:SI 2 "arith_operand" "K,Kr")
			 (match_operand:SI 3 "arith_operand" "K,&r")))]
  ""
  "*
{
  if (GET_CODE (operands[3]) == CONST_INT)
    return \"extu %0,%1,%2<%3>\";
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[2]) & 0x1f) << 5);
      return \"mask %3,%3,0x1f\;or %3,%3,%2\;extu %0,%1,%3\";
    }
  return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r,r")
	(zero_extract:SI (match_operand:SI 1 "register_operand" "r,r")
			 (match_operand:SI 2 "arith_operand" "K,Kr")
			 (match_operand:SI 3 "arith_operand" "K,&r")))]
  ""
  "*
{
  if (GET_CODE (operands[3]) == CONST_INT)
    return \"extu %0,%1,%2<%3>\";
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[2]) & 0x1f) << 5);
      return \"mask %3,%3,0x1f\;or %3,%3,%2\;extu %0,%1,%3\";
    }
  return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
}")

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
			 (match_operand:SI 1 "arith_operand" "K,K,&r")
			 (match_operand:SI 2 "arith_operand" "K,&r,&"))
	(const_int 0))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"clr %0,%0,%1<%2>\";
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[1]) & 0x1f) << 5);
      return \"mask %2,%2,0x1f\;or %2,%2,%1\;clr %0,%0,%2\";
    }
  return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;clr %0,%0,%2\";
}")

(define_insn ""
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
			 (match_operand:SI 1 "arith_operand" "K,K,&r")
			 (match_operand:SI 2 "arith_operand" "K,&r,&r"))
	(const_int -1))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"set %0,%0,%1<%2>\";
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[1]) & 0x1f) << 5);
      return \"mask %2,%2,0x1f\;or %2,%2,%1\;set %0,%0,%2\";
    }
  return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;set %0,%0,%2\";
}")

(define_insn "insv"
  [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
			 (match_operand:SI 1 "arith_operand" "K,K,&r")
			 (match_operand:SI 2 "arith_operand" "K,&r,&r"))
	(match_operand:SI 3 "register_operand" "&r,&r,r"))]
  ""
  "*
{
  if (GET_CODE (operands[2]) == CONST_INT)
    return \"mak %3,%3,%1<%2>\;clr %0,%0,%1<%2>\;or %0,%0,%3\";
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
			     (INTVAL (operands[1]) & 0x1f) << 5);
      return \"mask %2,%2,0x1f\;or %2,%2,%1\;mak %3,%3,%2\;clr %0,%0,%2\;or %0,%0,%3\";
    }
  return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;mak %1,%3,%2\;clr %0,%0,%2\;or %0,%0,%1\";
}")

;; negate insns
(define_insn "negsi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
  ""
  "sub %0,r0,%1")

(define_insn "negdf2"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(neg:DF (match_operand:DF 1 "register_operand" "r")))]
  ""
  "fsub.dsd %0,r0,%1")

(define_insn "negsf2"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(neg:SF (match_operand:SF 1 "register_operand" "r")))]
  ""
  "fsub.sss %0,r0,%1")

;; Store condition code values into registers
(define_insn "seq"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(eq (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[0]))
    return \"extu %0,r25,1<eq>\";
  return \"extu r25,r25,1<eq>\;st r25,%0\";
}")

(define_peephole
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
   (set (match_operand:SI 1 "general_operand" "=g")
	(eq (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[1]))
    return \"cmp r25,%0,0\;extu %1,r25,1<eq>\";
  return \"cmp r25,%0,0\;extu r25,r25,1<eq>\;st r25,%1\";
}")

(define_peephole
  [(set (cc0)
	(compare
	 (match_operand:SI 0 "arith_operand" "r")
	 (match_operand:SI 1 "arith_operand" "rI")))
   (set (match_operand:SI 2 "general_operand" "=g")
	(eq (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[2]))
    return \"cmp r25,%0,%1\;extu %2,r25,1<eq>\";
  return \"cmp r25,%0,%1\;extu r25,r25,1<eq>\;st r25,%2\";
}")

(define_insn "sne"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ne (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[0]))
    return \"extu %0,r25,1<ne>\";
  return \"extu r25,r25,1<ne>\;st r25,%0\";
}")

(define_peephole
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
   (set (match_operand:SI 1 "general_operand" "=g")
	(ne (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[1]))
    return \"cmp r25,%0,0\;extu %1,r25,1<ne>\";
  return \"cmp r25,%0,0\;extu r25,r25,1<ne>\;st r25,%1\";
}")

(define_peephole
  [(set (cc0)
	(compare
	 (match_operand:SI 0 "arith_operand" "r")
	 (match_operand:SI 1 "arith_operand" "rI")))
   (set (match_operand:SI 2 "general_operand" "=g")
	(ne (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[2]))
    return \"cmp r25,%0,%1\;extu %2,r25,1<ne>\";
  return \"cmp r25,%0,%1\;extu r25,r25,1<ne>\;st r25,%2\";
}")

(define_insn "sgt"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(gt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[0]))
    return \"extu %0,r25,1<gt>\";
  return \"extu r25,r25,1<gt>\;st r25,%0\";
}")

(define_peephole
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
   (set (match_operand:SI 1 "general_operand" "=g")
	(gt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[1]))
    return \"cmp r25,%0,0\;extu %1,r25,1<gt>\";
  return \"cmp r25,%0,0\;extu r25,r25,1<gt>\;st r25,%1\";
}")

(define_peephole
  [(set (cc0)
	(compare
	 (match_operand:SI 0 "arith_operand" "r")
	 (match_operand:SI 1 "arith_operand" "rI")))
   (set (match_operand:SI 2 "general_operand" "=g")
	(gt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[2]))
    return \"cmp r25,%0,%1\;extu %2,r25,1<gt>\";
  return \"cmp r25,%0,%1\;extu r25,r25,1<gt>\;st r25,%2\";
}")

(define_insn "sgtu"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(gtu (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[0]))
    return \"extu %0,r25,1<hi>\";
  return \"extu r25,r25,1<hi>\;st r25,%0\";
}")

(define_peephole
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
   (set (match_operand:SI 1 "general_operand" "=g")
	(gtu (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[1]))
    return \"cmp r25,%0,0\;extu %1,r25,1<hi>\";
  return \"cmp r25,%0,0\;extu r25,r25,1<hi>\;st r25,%1\";
}")

(define_peephole
  [(set (cc0)
	(compare
	 (match_operand:SI 0 "arith_operand" "r")
	 (match_operand:SI 1 "arith_operand" "rI")))
   (set (match_operand:SI 2 "general_operand" "=g")
	(gtu (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[2]))
    return \"cmp r25,%0,%1\;extu %2,r25,1<hi>\";
  return \"cmp r25,%0,%1\;extu r25,r25,1<hi>\;st r25,%2\";
}")

(define_insn "slt"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(lt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[0]))
    return \"extu %0,r25,1<lt>\";
  return \"extu r25,r25,1<lt>\;st r25,%0\";
}")

(define_peephole
  [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
   (set (match_operand:SI 1 "general_operand" "=g")
	(lt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[1]))
    return \"cmp r25,%0,0\;extu %1,r25,1<lt>\";
  return \"cmp r25,%0,0\;extu r25,r25,1<lt>\;st r25,%1\";
}")

(define_peephole
  [(set (cc0)
	(compare
	 (match_operand:SI 0 "arith_operand" "r")
	 (match_operand:SI 1 "arith_operand" "rI")))
   (set (match_operand:SI 2 "general_operand" "=g")
	(lt (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;
  if (REG_P (operands[2]))
    return \"cmp r25,%0,%1\;extu %2,r25,1<lt>\";
  return \"cmp r25,%0,%1\;extu r25,r25,1<lt>\;st r25,%2\";
}")

(define_insn "sltu"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ltu (cc0) (const_int 0)))]
  ""
  "*
{
  CC_STATUS_INIT;