m88k.md

这是完整的gcc源代码

  return \"st.b %1,%0\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "r")
	(sign_extend:SI
	  (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
			   (match_operand:SI 2 "arith_operand" "rI")))))
   (set (match_dup 1)
	(plus:SI (match_dup 1)
		 (match_dup 2)))]
  ""
  "ld.b %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "r")
	(zero_extend:SI
	  (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
			   (match_operand:SI 2 "arith_operand" "rI")))))
   (set (match_dup 1)
	(plus:SI (match_dup 1)
		 (match_dup 2)))]
  ""
  "ld.bu %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")

(define_insn ""
  [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
			 (match_operand:SI 1 "arith_operand" "rI")))
	(match_operand:SI 2 "register_operand" "r"))
   (set (match_dup 0)
	(plus:SI (match_dup 0)
		 (match_dup 1)))]
  ""
  "st.b %2,%0,%1\\t;; pipelined!\;addu %0,%0,%1\\t;; /")

;; The definition of this insn does not really explain what it does,
;; but it should suffice
;; that anything generated as this insn will be recognized as one
;; and that it won't successfully combine with anything.
(define_insn "movstrsi"
  [(set (match_operand:BLK 0 "general_operand" "=g")
	(match_operand:BLK 1 "general_operand" "g"))
   (use (match_operand:SI 2 "arith32_operand" "rn"))
   (clobber (reg:SI 10))
   (clobber (reg:SI 11))
   (clobber (reg:SI 12))]
  ""
  "* output_block_move (operands);")

;; This pattern forces (set (reg:DF ...) (const_double ...))
;; to be reloaded by putting the constant into memory.
;; It must come before the more general movdf pattern.
(define_insn ""
  [(set (match_operand:DF 0 "general_operand" "=r,o")
	(match_operand:DF 1 "" "mG,G"))]
  "GET_CODE (operands[1]) == CONST_DOUBLE"
  "*
{
  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == REG)
    {
      operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
      return \"add %0,r0,0\;add %1,r0,0\";
    }
  if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == MEM)
    {
      operands[1] = adj_offsettable_operand (operands[0], 4);
      return \"st r0,%0\;st r0,%1\";
    }
  return output_move_double (operands);
}
")
  
(define_insn "movdf"
  [(set (match_operand:DF 0 "general_operand" "=r,m")
	(match_operand:DF 1 "general_operand" "rm,r"))]
  ""
  "* return output_move_double (operands);")

(define_insn "movdi"
  [(set (match_operand:DI 0 "general_operand" "=r,m")
	(match_operand:DI 1 "general_operand" "rm,r"))]
  ""
  "* return output_move_double (operands);")

(define_insn "movsf"
  [(set (match_operand:SF 0 "general_operand" "=g,r")
	(match_operand:SF 1 "general_operand" "r,mF"))]
  ""
  "*
{
  if (REG_P (operands[0]))
    {
      if (GET_CODE (operands[1]) == MEM)
	return \"ld %0,%1\";
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
	return output_store_const_float (SFmode, operands);
      return \"or %0,r0,%1\";
    }
  return \"st %1,%0\";
}")

;;- load effective address 
(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:QI 1 "address_operand" "p"))]
  ""
  "lda.b %0,%a1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:HI 1 "address_operand" "p"))]
  ""
  "lda.w %0,%a1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:SI 1 "address_operand" "p"))]
  ""
  "lda %0,%a1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:DI 1 "address_operand" "p"))]
  ""
  "lda.d %0,%a1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:SF 1 "address_operand" "p"))]
  ""
  "lda %0,%a1")

(define_insn ""
  [(set (match_operand:SI 0 "register_operand" "=r")
	(match_operand:DF 1 "address_operand" "p"))]
  ""
  "lda.d %0,%a1")

;;- truncation instructions
(define_insn "truncsiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI
	 (match_operand:SI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    return \"st.b %1,%0\";
  return \"or %0,r0,%1\";
}")

(define_insn "trunchiqi2"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(truncate:QI
	 (match_operand:HI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    return \"st.b %1,%0\";
  return \"or %0,r0,%1\";
}")

(define_insn "truncsihi2"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(truncate:HI
	 (match_operand:SI 1 "register_operand" "r")))]
  ""
  "*
{
  if (GET_CODE (operands[0]) == MEM)
    return \"st.h %1,%0\";
  return \"or %0,r0,%1\";
}")

;;- zero extension instructions

;; Note that the one starting from HImode comes before those for QImode
;; so that a constant operand will match HImode, not QImode.

(define_insn "zero_extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI
	 (match_operand:HI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"mask %0,%1,0xffff\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.hu %0,%1\";
}")

(define_insn "zero_extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(zero_extend:HI
	 (match_operand:QI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"mask %0,%1,0xff\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.bu %0,%1\";
}")

(define_insn "zero_extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(zero_extend:SI
	 (match_operand:QI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"mask %0,%1,0xff\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.bu %0,%1\";
}")

;;- sign extension instructions
;; Note that the one starting from HImode comes before those for QImode
;; so that a constant operand will match HImode, not QImode.

(define_insn "extendhisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:HI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"ext %0,%1,16<0>\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.h %0,%1\";
}")

(define_insn "extendqihi2"
  [(set (match_operand:HI 0 "register_operand" "=r")
	(sign_extend:HI
	 (match_operand:QI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"ext %0,%1,8<0>\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.b %0,%1\";
}")

(define_insn "extendqisi2"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(sign_extend:SI
	 (match_operand:QI 1 "general_operand" "g")))]
  ""
  "*
{
  if (REG_P (operands[1]))
    return \"ext %0,%1,8<0>\";
  if (GET_CODE (operands[1]) == CONST_INT)
    return output_store_const_int (SImode, operands);
  return \"ld.b %0,%1\";
}")

;; Conversions between float and double.

(define_insn "extendsfdf2"
  [(set (match_operand:DF 0 "general_operand" "=r")
	(float_extend:DF
	 (match_operand:SF 1 "general_operand" "r")))]
  ""
  "fadd.dss %0,r0,%1")

(define_insn "truncdfsf2"
  [(set (match_operand:SF 0 "general_operand" "=r")
	(float_truncate:SF
	 (match_operand:DF 1 "general_operand" "r")))]
  ""
  "fadd.ssd %0,r0,%1")
;; Conversions between floating point and integer

(define_insn "floatsidf2"
  [(set (match_operand:DF 0 "general_operand" "=r")
	(float:DF (match_operand:SI 1 "general_operand" "r")))]
  ""
  "flt.ds %0,%1")

(define_insn "floatsisf2"
  [(set (match_operand:SF 0 "general_operand" "=r")
	(float:SF (match_operand:SI 1 "general_operand" "r")))]
  ""
  "flt.ss %0,%1")

(define_insn "fixdfsi2"
  [(set (match_operand:SI 0 "general_operand" "=r")
	(fix:SI (fix:DF (match_operand:DF 1 "general_operand" "r"))))]
  ""
  "int.sd %0,%1")

(define_insn "fixsfsi2"
  [(set (match_operand:SI 0 "general_operand" "=r")
	(fix:SI (fix:SF (match_operand:SF 1 "general_operand" "r"))))]
  ""
  "int.ss %0,%1")

;;- arithmetic instructions
;;- add instructions
(define_insn "addsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(plus:SI (match_operand:SI 1 "arith32_operand" "%r")
		 (match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"addu %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"addu %0,%1,%2\";
  if (INT_FITS_16_BITS (-i))
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode, -i);
      return \"subu %0,%1,%2\";
    }
  return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;addu %0,%1,%0\";
}")

(define_insn "adddf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(plus:DF (match_operand:DF 1 "register_operand" "%r")
		 (match_operand:DF 2 "register_operand" "r")))]
  ""
  "fadd.ddd %0,%1,%2")

;; a bunch more can go in here!

(define_insn "addsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(plus:SF (match_operand:SF 1 "register_operand" "%r")
		 (match_operand:SF 2 "register_operand" "r")))]
  ""
  "fadd.sss %0,%1,%2")

;;- subtract instructions
(define_insn "subsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(minus:SI (match_operand:SI 1 "register_operand" "r")
		  (match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"subu %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"subu %0,%1,%2\";
  if (INT_FITS_16_BITS (-i))
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode, -i);
      return \"addu %0,%1,%2\";
    }
  return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;subu %0,%1,%0\";
}")

(define_insn "subdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(minus:DF (match_operand:DF 1 "register_operand" "%r")
		  (match_operand:DF 2 "register_operand" "r")))]
  ""
  "fsub.ddd %0,%1,%2")

(define_insn "subsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(minus:SF (match_operand:SF 1 "register_operand" "%r")
		  (match_operand:SF 2 "register_operand" "r")))]
  ""
  "fsub.sss %0,%1,%2")

;;- multiply instructions
(define_insn "mulsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mult:SI (match_operand:SI 1 "register_operand" "%r")
		 (match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"mul %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"mul %0,%1,%2\";
  return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;mul %0,%1,%0\";
}")

(define_insn "umulsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(umult:SI (match_operand:SI 1 "register_operand" "%r")
		  (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "mul %0,%1,%2")

(define_insn "muldf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(mult:DF (match_operand:DF 1 "register_operand" "%r")
		 (match_operand:DF 2 "register_operand" "r")))]
  ""
  "fmul.ddd %0,%1,%2")

(define_insn "mulsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(mult:SF (match_operand:SF 1 "register_operand" "%r")
		 (match_operand:SF 2 "register_operand" "r")))]
  ""
  "fmul.sss %0,%1,%2")

;;- divide instructions
(define_insn "divsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(div:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"div %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"div %0,%1,%2\";
  return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;div %0,%1,%0\";
}")


(define_insn "udivsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(udiv:SI (match_operand:SI 1 "register_operand" "r")
		 (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "div %0,%1,%2")

(define_insn "divdf3"
  [(set (match_operand:DF 0 "register_operand" "=r")
	(div:DF (match_operand:DF 1 "register_operand" "r")
		(match_operand:DF 2 "register_operand" "r")))]
  ""
  "fdiv.ddd %0,%1,%2")

(define_insn "divsf3"
  [(set (match_operand:SF 0 "register_operand" "=r")
	(div:SF (match_operand:SF 1 "register_operand" "r")
		(match_operand:SF 2 "register_operand" "r")))]
  ""
  "fdiv.sss %0,%1,%2")

;; Remainder instructions.

(define_insn "modsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(mod:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
  if (INT_FITS_16_BITS (-i))
    fatal (\"implement negative case for mod\");
  fatal (\"implement 32 bit case for mod\");
}")

(define_insn "umodsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(umod:SI (match_operand:SI 1 "register_operand" "r")
		 (match_operand:SI 2 "arith_operand" "rI")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
  if (INT_FITS_16_BITS (-i))
    fatal (\"implement negative case for umod\");
  fatal (\"implement 32 bit case for umod\");
}")

(define_insn "divmodsi4"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(div:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "arith_operand" "rI")))
   (set (match_operand:SI 3 "register_operand" "=r")
	(mod:SI (match_dup 1) (match_dup 2)))]
  ""
  "div %0,%1,%2\;mul %3,%0,%2\;sub %3,%1,%3")

(define_insn "udivmodsi4"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(udiv:SI (match_operand:SI 1 "register_operand" "r")
		(match_operand:SI 2 "arith_operand" "rI")))
   (set (match_operand:SI 3 "register_operand" "=r")
	(umod:SI (match_dup 1) (match_dup 2)))]
  ""
  "div %0,%1,%2\;mul %3,%0,%2\;sub %3,%1,%3")

;;- and instructions (with complement also)
(define_insn "andsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"and %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"mask %0,%1,%2\";
  if (INT_FITS_16_BITS (-i))
    {
      operands[2] = gen_rtx (CONST_INT, VOIDmode, i & 0xffff);
      return \"and %0,%1,%2\";
    }
  return \"and.u %0,%1,hi16(%2)\;and %0,%1,lo16(%2)\";
}")

(define_insn "andcbsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(and:SI (match_operand:SI 1 "register_operand" "%r")
		(not:SI (match_operand:SI 2 "register_operand" "r"))))]
  ""
  "and.c %0,%1,%2")

;;- Bit set (inclusive or) instructions (with complement also)
(define_insn "iorsi3"
  [(set (match_operand:SI 0 "register_operand" "=r")
	(ior:SI (match_operand:SI 1 "register_operand" "%r")
		(match_operand:SI 2 "arith32_operand" "rn")))]
  ""
  "*
{
  unsigned int i;

  if (REG_P (operands[2]))
    return \"or %0,%1,%2\";
  i = INTVAL (operands[2]);
  if (INT_FITS_16_BITS (i))
    return \"or %0,%1,%2\";
  return \"or.u %0,%1,hi16(%2)\;or %0,%1,lo16(%2)\";