ns32k.md

这是完整的gcc源代码

  "
{
  operands[2] = negate_rtx (SImode, operands[2]);
}")

(define_expand "lshrqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(lshift:QI (match_operand:QI 1 "general_operand" "g")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "
{
  operands[2] = negate_rtx (SImode, operands[2]);
}")

;; Rotate instructions

(define_insn "rotlsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(rotate:SI (match_operand:SI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "rmn")))]
  ""
  "rotd %2,%0")

(define_insn "rotlhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(rotate:HI (match_operand:HI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "rmn")))]
  ""
  "rotw %2,%0")

(define_insn "rotlqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(rotate:QI (match_operand:QI 1 "general_operand" "0")
		   (match_operand:SI 2 "general_operand" "rmn")))]
  ""
  "rotb %2,%0")

;; Right rotate on the 32k works by negating the shift count.
(define_expand "rotrsi3"
  [(set (match_operand:SI 0 "general_operand" "=g")
	(rotate:SI (match_operand:SI 1 "general_operand" "g")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "
{
  operands[2] = negate_rtx (SImode, operands[2]);
}")

(define_expand "rotrhi3"
  [(set (match_operand:HI 0 "general_operand" "=g")
	(rotate:HI (match_operand:HI 1 "general_operand" "g")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "
{
  operands[2] = negate_rtx (SImode, operands[2]);
}")

(define_expand "rotrqi3"
  [(set (match_operand:QI 0 "general_operand" "=g")
	(rotate:QI (match_operand:QI 1 "general_operand" "g")
		   (match_operand:SI 2 "general_operand" "g")))]
  ""
  "
{
  operands[2] = negate_rtx (SImode, operands[2]);
}")

;;- load or push effective address 
;; These come after the move, add, and multiply patterns
;; because we don't want pushl $1 turned into pushad 1.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g<")
	(match_operand:QI 1 "address_operand" "p"))]
  ""
  "*
{
  if (REG_P (operands[0])
      && GET_CODE (operands[1]) == MULT
      && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
      && (INTVAL (XEXP (operands[1], 1)) == 2
	  || INTVAL (XEXP (operands[1], 1)) == 4))
    {
      rtx xoperands[3];
      xoperands[0] = operands[0];
      xoperands[1] = XEXP (operands[1], 0);
      xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
      return output_shift_insn (xoperands);
    }
  return \"addr %a1,%0\";
}")

;;; Index insns.  These are about the same speed as multiply-add counterparts.
;;; but slower then using power-of-2 shifts if we can use them
;
;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;	(plus:SI (match_operand:SI 1 "general_operand" "rmn")
;		 (mult:SI (match_operand:SI 2 "register_operand" "0")
;			  (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
;  "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
;  "indexd %0,%3,%1")
;
;(define_insn ""
;  [(set (match_operand:SI 0 "register_operand" "=r")
;	(plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
;			  (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
;		 (match_operand:SI 3 "general_operand" "rmn")))]
;  "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
;  "indexd %0,%2,%3")

;; Set, Clear, and Invert bit

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ior:SI
	 (ashift:SI (const_int 1)
		    (match_operand:SI 1 "general_operand" "rmn"))
	 (match_dup 0)))]
  ""
  "sbitd %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(ior:SI
	 (match_dup 0)
	 (ashift:SI (const_int 1)
		    (match_operand:SI 1 "general_operand" "rmn"))))]
  ""
  "sbitd %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(ior:QI
	 (subreg:QI
	  (ashift:SI (const_int 1)
		     (match_operand:QI 1 "general_operand" "rmn")) 0)
	 (match_dup 0)))]
  ""
  "sbitb %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(ior:QI
	 (match_dup 0)
	 (subreg:QI
	  (ashift:SI (const_int 1)
		     (match_operand:QI 1 "general_operand" "rmn")) 0)))]
  ""
  "sbitb %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(and:SI
	 (not:SI
	  (ashift:SI (const_int 1)
		     (match_operand:SI 1 "general_operand" "rmn")))
	 (match_dup 0)))]
  ""
  "cbitd %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(and:SI
	 (match_dup 0)
	 (not:SI
	  (ashift:SI (const_int 1)
		     (match_operand:SI 1 "general_operand" "rmn")))))]
  ""
  "cbitd %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(and:QI
	 (subreg:QI
	  (not:SI
	   (ashift:SI (const_int 1)
		      (match_operand:QI 1 "general_operand" "rmn"))) 0)
	 (match_dup 0)))]
  ""
  "cbitb %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(and:QI
	 (match_dup 0)
	 (subreg:QI
	  (not:SI
	   (ashift:SI (const_int 1)
		      (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
  ""
  "cbitb %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(xor:SI
	 (ashift:SI (const_int 1)
		    (match_operand:SI 1 "general_operand" "rmn"))
	 (match_dup 0)))]
  ""
  "ibitd %1,%0")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g")
	(xor:SI
	 (match_dup 0)
	 (ashift:SI (const_int 1)
		    (match_operand:SI 1 "general_operand" "rmn"))))]
  ""
  "ibitd %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(xor:QI
	 (subreg:QI
	  (ashift:SI (const_int 1)
		     (match_operand:QI 1 "general_operand" "rmn")) 0)
	 (match_dup 0)))]
  ""
  "ibitb %1,%0")

(define_insn ""
  [(set (match_operand:QI 0 "general_operand" "=g")
	(xor:QI
	 (match_dup 0)
	 (subreg:QI
	  (ashift:SI (const_int 1)
		     (match_operand:QI 1 "general_operand" "rmn")) 0)))]
  ""
  "ibitb %1,%0")

;; Recognize jbs and jbc instructions.

(define_insn ""
  [(set (cc0)
	(zero_extract (match_operand:SI 0 "general_operand" "rm")
		      (const_int 1)
		      (match_operand:SI 1 "general_operand" "rmn")))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_F;
  return \"tbitd %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
			       (const_int 1)
			       (match_operand:SI 1 "general_operand" "rmn"))
		 (const_int 1)))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_NOT_F;
  return \"tbitd %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(zero_extract (match_operand:HI 0 "general_operand" "rm")
		      (const_int 1)
		      (match_operand:HI 1 "general_operand" "g")))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_F;
  return \"tbitw %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(compare (zero_extract (match_operand:HI 0 "general_operand" "rm")
			       (const_int 1)
			       (match_operand:HI 1 "general_operand" "g"))
		 (const_int 1)))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_NOT_F;
  return \"tbitw %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(zero_extract (match_operand:QI 0 "general_operand" "rm")
		      (const_int 1)
		      (match_operand:QI 1 "general_operand" "g")))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_F;
  return \"tbitb %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(compare (zero_extract:SI (match_operand:QI 0 "general_operand" "rm")
				  (const_int 1)
				  (match_operand:QI 1 "general_operand" "rmn"))
		 (const_int 1)))]
  ""
  "*
{ cc_status.flags = CC_Z_IN_NOT_F;
  return \"tbitb %1,%0\";
}")

(define_insn ""
  [(set (cc0)
	(and:SI (match_operand:SI 0 "general_operand" "rm")
		(match_operand:SI 1 "immediate_operand" "i")))]
  "GET_CODE (operands[1]) == CONST_INT
   && exact_log2 (INTVAL (operands[1])) >= 0"
  "*
{
  operands[1]
    = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
  cc_status.flags = CC_Z_IN_F;
  return \"tbitd %1,%0\";
}")

;; extract(base, width, offset)
;; Signed bitfield extraction is not supported in hardware on the
;; NS 32032.  It is therefore better to let GCC figure out a
;; good strategy for generating the proper instruction sequence
;; and represent it as rtl.

;; Optimize the case of extracting a byte or word from a register.
;; Otherwise we must load a register with the offset of the
;; chunk we want, and perform an extract insn (each of which
;; is very expensive).  Since we use the stack to do our bit-twiddling
;; we cannot use it for a destination.  Perhaps things are fast
;; enough on the 32532 that such hacks are not needed.

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=ro")
	(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
			 (match_operand:SI 2 "const_int" "i")
			 (match_operand:SI 3 "const_int" "i")))]
  "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
   && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
  "*
{
  output_asm_insn (\"movd %1,tos\", operands);
  if (INTVAL (operands[2]) == 16)
    {
      if (INTVAL (operands[3]) == 8)
	output_asm_insn (\"movzwd 1(sp),%0\", operands);
      else
	output_asm_insn (\"movzwd 2(sp),%0\", operands);
    }
  else
    {
      if (INTVAL (operands[3]) == 8)
	output_asm_insn (\"movzbd 1(sp),%0\", operands);
      else if (INTVAL (operands[3]) == 16)
	output_asm_insn (\"movzbd 2(sp),%0\", operands);
      else
	output_asm_insn (\"movzbd 3(sp),%0\", operands);
    }
  return \"cmpqd %$0,tos\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=ro")
	(zero_extract:SI (match_operand:HI 1 "register_operand" "r")
			 (match_operand:SI 2 "const_int" "i")
			 (match_operand:SI 3 "const_int" "i")))]
  "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
  "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")

(define_insn "extzv"
  [(set (match_operand:SI 0 "general_operand" "=g<,g<")
	(zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
			 (match_operand:SI 2 "const_int" "i,i")
			 (match_operand:SI 3 "general_operand" "rK,n")))]
  ""
  "*
{ if (GET_CODE (operands[3]) == CONST_INT)
    {
      if (INTVAL (operands[3]) >= 8)
	operands[1] = adj_offsettable_operand (operands[1],
					       INTVAL (operands[3]) >> 3);
      return \"extsd %1,%0,%3,%2\";
    }
  else return \"extd %3,%1,%0,%2\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g<,g<")
	(zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
			 (match_operand:SI 2 "const_int" "i,i")
			 (match_operand:SI 3 "general_operand" "rK,n")))]
  ""
  "*
{ if (GET_CODE (operands[3]) == CONST_INT)
    {
      if (INTVAL (operands[3]) >= 8)
	operands[1] = adj_offsettable_operand (operands[1],
					       INTVAL (operands[3]) >> 3);
      return \"extsd %1,%0,%3,%2\";
    }
  else return \"extd %3,%1,%0,%2\";
}")

(define_insn ""
  [(set (match_operand:SI 0 "general_operand" "=g<")
	(zero_extract:SI (match_operand:QI 1 "general_operand" "g")
			 (match_operand:SI 2 "const_int" "i")
			 (match_operand:SI 3 "general_operand" "rn")))]
  ""
  "*
{ if (GET_CODE (operands[3]) == CONST_INT)
    return \"extsd %1,%0,%3,%2\";
  else return \"extd %3,%1,%0,%2\";
}")

(define_insn "insv"
  [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
			 (match_operand:SI 1 "const_int" "i,i")
			 (match_operand:SI 2 "general_operand" "rK,n"))
	(match_operand:SI 3 "general_operand" "rm,rm"))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
	{
	  operands[0] = adj_offsettable_operand (operands[0],
					        INTVAL (operands[2]) / 8);
          operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
	}
      if (INTVAL (operands[1]) <= 8)
	return \"inssb %3,%0,%2,%1\";
      else if (INTVAL (operands[1]) <= 16)
	return \"inssw %3,%0,%2,%1\";
      else
	return \"inssd %3,%0,%2,%1\";
    }
  return \"insd %2,%3,%0,%1\";
}")

(define_insn ""
  [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
			 (match_operand:SI 1 "const_int" "i,i")
			 (match_operand:SI 2 "general_operand" "rK,n"))
	(match_operand:SI 3 "general_operand" "rm,rm"))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
	{
	  operands[0] = adj_offsettable_operand (operands[0],
					         INTVAL (operands[2]) / 8);
          operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
	}
      if (INTVAL (operands[1]) <= 8)
	return \"inssb %3,%0,%2,%1\";
      else if (INTVAL (operands[1]) <= 16)
	return \"inssw %3,%0,%2,%1\";
      else
	return \"inssd %3,%0,%2,%1\";
    }
  return \"insd %2,%3,%0,%1\";
}")

(define_insn ""
  [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
			 (match_operand:SI 1 "const_int" "i")
			 (match_operand:SI 2 "general_operand" "rn"))
	(match_operand:SI 3 "general_operand" "rm"))]
  ""
  "*
{ if (GET_CODE (operands[2]) == CONST_INT)
    if (INTVAL (operands[1]) <= 8)
      return \"inssb %3,%0,%2,%1\";
    else if (INTVAL (operands[1]) <= 16)
      return \"inssw %3,%0,%2,%1\";
    else
      return \"inssd %3,%0,%2,%1\";
  return \"insd %2,%3,%0,%1\";
}")


(define_insn "jump"
  [(set (pc)
	(label_ref (match_operand 0 "" "")))]
  ""
  "br %l0")

(define_insn "beq"
  [(set (pc)
	(if_then_else (eq (cc0)
			  (const_int 0))
		      (label_ref (match_operand 0 "" ""))
		      (pc)))]
  ""
  "*
{ if (cc_prev_status.flags & CC_Z_IN_F)
    return \"bfc %l0\";
  else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
    return \"bfs %l0\";
  else return \"beq %l0\";
}")

(define_insn "bne"
  [(set (pc)
	(if_then_else (ne (cc0)