cpldleifei.txt

CPLD的无线数据传输模块开发

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ramtime5 is
        port(   a15 : in  STD_LOGIC; --inputs to be prioritised
                a14 : in  STD_LOGIC;
                a13 : in  STD_LOGIC;
                a10 : in  STD_LOGIC;
                a9  : in  STD_LOGIC;
                a8  : in  STD_LOGIC;
                rd  : in  STD_LOGIC;
                wr  : in  STD_LOGIC;
                clk : in  STD_LOGIC;
                rst : in  STD_LOGIC;

                d0 : in STD_LOGIC;
                d1 : in STD_LOGIC;
                d2 : in STD_LOGIC;
                d3 : in STD_LOGIC;

                d4 : in STD_LOGIC;
                d5 : in STD_LOGIC;
                d6 : in STD_LOGIC;
                d7 : in STD_LOGIC;

                am040_rd:out STD_LOGIC;
                am040_cp:out STD_LOGIC;
                u11_cp  :out STD_LOGIC;
                u12_oe  : out STD_LOGIC;
                a18_out : buffer STD_LOGIC;
                a17_out : buffer STD_LOGIC;
                a16_out : buffer STD_LOGIC;
                sd      : out STD_LOGIC;
                sck     : out STD_LOGIC;
                ram_rd  : out STD_LOGIC; --encoded output
                ram_wr  : out STD_LOGIC --group signal output 
            );
end ramtime5;
architecture v1 of ramtime5 is

      --  SIGNAL sh_t1: STD_LOGIC;
      --  signal sh_t2: std_logic;
      --  signal sh_t3: std_logic;
        SIGNAL d_s0 : STD_LOGIC;
        SIGNAL d_s1 : STD_LOGIC;
        SIGNAL d_s2 : STD_LOGIC;
        SIGNAL d_s3 : STD_LOGIC;
        SIGNAL d_s4 : STD_LOGIC;
        SIGNAL d_s5 : STD_LOGIC;
        SIGNAL d_s6 : STD_LOGIC;
        SIGNAL d_s7 : STD_LOGIC;
        SIGNAL dill   : STD_LOGIC;
       -- signal doll   : std_logic; 
        signal count  : std_logic_vector(6 downto 0);
       -- qa		: OUT 	INTEGER RANGE 0 TO 63;
 
 begin 
            ram_rd  <= a15 or rd;
            ram_wr  <= a15 or wr;
            u12_oe  <= not a15 or a14 or not a13 or rd;
            am040_rd<= not a15 or not a14 or a13 or rd;
            u11_cp  <= not a15 or not a14 or a13 or wr;

            --sd      <= count(2);
            --am040_cp<= not a15 or a14 or a13 or wr;


    G1:     PROCESS(a15,a14,a13,wr,rst)
                begin
                  if(rst='1')then 
                     a16_out <= '0';
                     a17_out <= '0';
                     a18_out <= '0';
                     am040_cp<= '1';
                  elsIF(a15='0' or a14='1' or a13='1' or rd='0' OR wr='1')THEN
                     am040_cp <='1';
                     
                  elsif( WR='0') then
                     a16_out <= a8;
                     a17_out <= a9;
                     a18_out <= a10;                 
                     am040_cp<= '0'; 
                  end if;
             end process;      --OK!





    G2:      process(wr,clk)
                   variable dil : std_logic;
                   variable d_d : std_logic_vector(7 downto 0);
                 begin
                  if(clk'event and clk='1')then
                       if(a15='1' and a14='0' and a13='1' and  wr='0')then
                         d_d(0) := d0; --and a15 and not a14 and a13 and not wr;
                         d_d(1) := d1; --and a15 and not a14 and a13 and not wr;
                         d_d(2) := d2;--and a15 and not a14 and a13 and not wr;
                         d_d(3) := d3; --and a15 and not a14 and a13 and not wr;
                         d_d(4) := d4;--and a15 and not a14 and a13 and not wr;
                         d_d(5) := d5; --and a15 and not a14 and a13 and not wr;
                         d_d(6) := d6; --and a15 and not a14 and a13 and not wr;
                         d_d(7) := d7; --and a15 and not a14 and a13 and not wr;
                         dil :='1';
                         d_s0 <=d_d(0);
                         d_s1 <=d_d(1);
                         d_s2 <=d_d(2);
                         d_s3 <=d_d(3);
                         d_s4 <=d_d(4); 
                         d_s5 <=d_d(5);
                         d_s6 <=d_d(6);
                         d_s7 <=d_d(7);                   
                      elsif(count(6)='1')then
                         dil :='0';
                      end if;
                         dill <=dil;
                  end if;
               end process;



 G3:      PROCESS (clk,wr,rst)
		          VARIABLE    cnt	: std_logic_vector(6 downto 0);
	           BEGIN
                     IF ((a15='1' and a14='0' and a13='1' and  wr='0')or rst='1') THEN
                          cnt := "0000000";
			          elsIF (clk'event and clk='1') THEN
                           if(cnt(6) = '0' and dill='1')then   --技巧:判断COUNT仿止反复计数
			                cnt := cnt + 1;
                           
   			               END IF;
		            END IF;	
                          count <= cnt;
	         END PROCESS;



   G4:    process(count,clk,count(2),rst)
               begin
                 --if(clk'event and clk='1')then
                 if(dill='0' or rst='1' or count(2)='0')then
                      --sd <= '0';
                      sck<= '0';     
                 elsif(count(2)='1' and count(3)='0' and count(4)='0' and count(5)='0' and count(6)='0')then
                     --sd<=d_s0;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='1' and count(4)='0' and count(5)='0' and count(6)='0')then
                     --sd<=d_s1;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='0' and count(4)='1' and count(5)='0' and count(6)='0')then
                     --sd<=d_s2;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='1' and count(4)='1' and count(5)='0' and count(6)='0')then
                     --sd<=d_s3;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='0' and count(4)='0' and count(5)='1' and count(6)='0')then
                     --sd<=d_s4;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='1' and count(4)='0' and count(5)='1' and count(6)='0')then
                     --sd<=d_s5;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='0' and count(4)='1' and count(5)='1' and count(6)='0')then
                     --sd<=d_s6;
                     sck<='1';
                 elsif(count(2)='1' and count(3)='1' and count(4)='1' and count(5)='1' and count(6)='0')then
                     --sd<=d_s7;
                     sck<='1';
                 end if;
                 
                 
                 --end if;
          end process;
 

     G5:    process(count,clk,count(2),rst)
               begin
                 --if(clk'event and clk='1')then
                 if(dill='0' or rst='1')then
                      sd <= '0';
                      --sck<= '0';     
                 elsif(count(3)='0' and count(4)='0' and count(5)='0' and count(6)='0')then
                     sd<=d_s0;
                     --sck<='1' after ;
                 elsif(count(3)='1' and count(4)='0' and count(5)='0' and count(6)='0')then
                     sd<=d_s1;
                     --sck<='1';
                 elsif(count(3)='0' and count(4)='1' and count(5)='0' and count(6)='0')then
                     sd<=d_s2;
                     --sck<='1';
                 elsif(count(3)='1' and count(4)='1' and count(5)='0' and count(6)='0')then
                     sd<=d_s3;
                     --sck<='1';
                 elsif(count(3)='0' and count(4)='0' and count(5)='1' and count(6)='0')then
                     sd<=d_s4;
                     --sck<='1';
                 elsif(count(3)='1' and count(4)='0' and count(5)='1' and count(6)='0')then
                     sd<=d_s5;
                     --sck<='1';
                 elsif(count(3)='0' and count(4)='1' and count(5)='1' and count(6)='0')then
                     sd<=d_s6;
                     --sck<='1';
                 elsif(count(3)='1' and count(4)='1' and count(5)='1' and count(6)='0')then
                     sd<=d_s7;
                     --sck<='1';
                 end if;
                 
                 
                 --end if;
          end process;

    end v1;