usrcomm.bak

此源码是用的NEC公司的MCU78F0396

#ifndef __USRCOMM_H__
#define __USRCOMM_H__


#pragma sfr
#pragma asm
#pragma di
#pragma ei
#pragma NOP
#pragma HALT
#pragma STOP



#define SYS_BEEP        P7.0        
#define SYS_ALARMLIGHT  P0.1   


/* data type defintion */
typedef unsigned long ULONG;
typedef unsigned int UINT;
typedef unsigned short USHORT;
typedef unsigned char UCHAR;
typedef unsigned char BOOL;

 

#define ON 1
#define OFF 0
#define TRUE 1
#define FALSE 0
#define IDLE 0 /* idle status */
#define READ 1 /* read mode */
#define WRITE 2 /* write mode */
#define SET 1
#define CLEAR 0
#define MD_STATUS unsigned short
#define MD_STATUSBASE 0x0
/* status list definition */
#define MD_OK MD_STATUSBASE+0x0 /* register setting OK */
#define MD_RESET MD_STATUSBASE+0x1 /* reset input */
#define MD_SENDCOMPLETE MD_STATUSBASE+0x2 /* send data complete */

/* error list definition */
#define MD_ERRORBASE        0x80
#define MD_ERROR            MD_ERRORBASE+0x0 /* error */
#define MD_RESOURCEERROR    MD_ERRORBASE+0x1 /* no resource available */
#define MD_PARITYERROR      MD_ERRORBASE+0x2 /* UARTn parity error */
#define MD_OVERRUNERROR     MD_ERRORBASE+0x3 /* UARTn overrun error */
#define MD_FRAMEERROR       MD_ERRORBASE+0x4 /* UARTn frame error */
#define MD_ARGERROR         MD_ERRORBASE+0x5 /* Error agrument input error */
#define MD_TIMINGERROR      MD_ERRORBASE+0x6 /* Error timing operation error */
#define MD_SETPROHIBITED    MD_ERRORBASE+0x7 /* setting prohibited */
#define MD_DATAEXISTS       MD_ERRORBASE+0x8 /* Data to be transferred next exists in TXBn register */
#define MD_SPT              MD_STATUSBASE+0x8 /*IIC stop*/
#define MD_NACK             MD_STATUSBASE+0x9 /*IIC no ACK*/
#define MD_SLAVE_SEND_END   MD_STATUSBASE+0x10 /*IIC slave send end*/
#define MD_SLAVE_RCV_END    MD_STATUSBASE+0x11 /*IIC slave receive end*/
#define MD_MASTER_SEND_END  MD_STATUSBASE+0x12 /*IIC master send end*/
#define MD_MASTER_RCV_END   MD_STATUSBASE+0x13 /*IIC master receive end*/
/* main clock and subclock as clock source */
enum ClockMode { HiRingClock, SysClock };
/* the value for IMS and IXS */
#define MEMORY_IMS_SET     0xCC
#define MEMORY_IXS_SET     0x00
/* clear IO register bit and set IO register bit */
#define ClrIORBit(Reg, ClrBitMap) Reg &= ~ClrBitMap
#define SetIORBit(Reg, SetBitMap) Reg |= SetBitMap
enum INTLevel { Highest, Lowest };
#define SYSTEMCLOCK     8000000
#define SUBCLOCK        32768
#define MAINCLOCK       8000000
#define FRCLOCK         8000000
#define FRCLOCKLOW      240000

//PORT O

#define P00   0
#define P01   1
#define P02   2
#define P03   3
#define P04   4
#define P05   5
#define P06   6
#define P07   7

#define PM00   0 
#define PM01   1 
#define PM02   2 
#define PM03   3 
#define PM04   4 
#define PM05   5 
#define PM06   6 
#define PM07   7 
//===================================================
//CSIM11  FF88H
#define CSOT11    0
#define DIR11     4
#define SSE11     5
#define TRMD11    6
#define CSIE11    7

#define CSIM11_CSIE11  (1 << CSIE11)
#define CSIM11_TRMD11  (1 << TRMD11)
#define CSIM11_SSE11   (1 << SSE11 )
#define CSIM11_DIR11   (1 << DIR11 )
#define CSIM11_CSOT11  (1 << CSOT11)

//CSIC11 FF89H
#define CKS110     0
#define CKS111     1
#define CKS112     2
#define DAP11      3
#define CKP11      4

#define CSIC11_CKS110  (1 << CKS110)
#define CSIC11_CKS111  (1 << CKS111)
#define CSIC11_CKS112  (1 << CKS112)
#define CSIC11_DAP11   (1 << DAP11 )
#define CSIC11_CKP11   (1 << CKP11 )

//===================================================
//IF1H Address: FFE3H After reset: 00H R/W
//XXIFX Interrupt request flag
//0     No interrupt request signal is generated
//1     Interrupt request is generated, interrupt request status
//===================================================
#define  IF1H_IICIF0  0x01   
#define  IF1H_CSIIF11 0x02
#define  IF1H_TMIF001 0x04
#define  IF1H_TMIF011 0x08

#endif