tmmmio.h

wince host 和 target PCI驱动程序

/*---------------------------------------------------------------------------- 
COPYRIGHT (c) 1995 by Philips Semiconductors

THIS SOFTWARE IS FURNISHED UNDER A LICENSE AND MAY ONLY BE USED AND COPIED IN 
ACCORDANCE WITH THE TERMS AND CONDITIONS OF SUCH A LICENSE AND WITH THE 
INCLUSION OF THE THIS COPY RIGHT NOTICE. THIS SOFTWARE OR ANY OTHER COPIES 
OF THIS SOFTWARE MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE TO ANY OTHER
PERSON. THE OWNERSHIP AND TITLE OF THIS SOFTWARE IS NOT TRANSFERRED. 

THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT ANY PRIOR NOTICE
AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY Philips Semiconductor. 

PHILIPS ASSUMES NO RESPONSIBILITY FOR THE USE OR RELIABILITY OF THIS SOFTWARE
ON PLATFORMS OTHER THAN THE ONE ON WHICH THIS SOFTWARE IS FURNISHED.
----------------------------------------------------------------------------*/

/*
ABSTRACT
The TriMedia hardware abstraction layer. This layer contains all the details

HISTORY
#define TR	Tilakraj Roy
960724	TR	Pulled out of tmhal.h 

*/

#ifndef	__TMMMIO_H__
#define __TMMMIO_H__

#define	TMHAL_INT_PRIORITY_LEVEL0	0
#define	TMHAL_INT_PRIORITY_LEVEL1	1
#define	TMHAL_INT_PRIORITY_LEVEL2	2
#define	TMHAL_INT_PRIORITY_LEVEL3	3
#define	TMHAL_INT_PRIORITY_LEVEL4	4
#define	TMHAL_INT_PRIORITY_LEVEL5	5
#define	TMHAL_INT_PRIORITY_LEVEL6	6
#define	TMHAL_INT_NON_MASKABLE		7

#define TMHAL_BIU_CONTROL_SE    0x0001
#define TMHAL_BIU_CONTROL_BO    0x0002
#define TMHAL_BIU_CONTROL_IE    0x0100
#define TMHAL_BIU_CONTROL_HE    0x0200
#define TMHAL_BIU_CONTROL_CR    0x0400
#define TMHAL_BIU_CONTROL_SR    0x0800


#define	TMHAL_DC_LOCK_CTL_HD	0x00000020
#define	TMHAL_DC_LOCK_CTL_HOLE_CTL	0x00000060

#define	TMHAL_HOLE_CTL_HEN	0x0	/* HOLE ENABLE */
#define	TMHAL_HOLE_CTL_HDS	0x1	/* HOLE DISABLE */
#define	TMHAL_HOLE_CTL_PDS	0x2 /* PCI DSIABLE */
#define	TMHAL_HOLE_CTL_RES	0x3	/* RESERVED */


typedef struct	_TMHAL_MMIO_VIC
{
	DWORD	volatile dwExeVec;

	DWORD	volatile dwDummy1[3];

	DWORD	volatile dwISetting[4];
	DWORD	volatile dwIPending;
	DWORD	volatile dwIClear;
	DWORD	volatile dwIMask;

	DWORD	volatile dwDummy2[0x15];

	DWORD	volatile dwIntVect[0x20];
}	TMHAL_MMIO_VIC, *PTMHAL_MMIO_VIC;


typedef struct _TMHAL_MMIO_TIMERS
{
	struct
	{
		DWORD	volatile dwTModulus;
		DWORD	volatile dwTValue;
		DWORD	volatile dwTControl;
		DWORD	volatile dwDummy[7];
	}	Registers[4];

}	TMHAL_MMIO_TIMERS, *PTMHAL_MMIO_TIMERS;



typedef struct	_TM_MMIO_DEBUG
{
	DWORD	volatile dwBIControl;
	DWORD	volatile dwBInstLow;
	DWORD	volatile dwBInstHigh;
	DWORD	volatile dwDummy[0x7];
	DWORD	volatile dwBDataLow;
	DWORD	volatile dwBDataHigh;
	DWORD	volatile dwBDataVal;
	DWORD	volatile dwBDataMask;
	DWORD	volatile dwBDControl;

} 	TMHAL_MMIO_DEBUG, *PTMHAL_MMIO_DEBUG;

/* made from specs version 950724 */

typedef struct	_TM_MMIO_BIU
{
	DWORD	volatile dwBIUStatus;
	DWORD	volatile dwBIUControl;
	DWORD	volatile dwPCIAddress;
	DWORD	volatile dwPCIData;

	DWORD	volatile dwConfigAddress;
	DWORD	volatile dwConfigData;
	DWORD	volatile dwConfigControl;

	DWORD	volatile dwIOAddress;
	DWORD	volatile dwIOData;
	DWORD	volatile dwIIOControl;

	DWORD	volatile dwSourceRegister;
	DWORD	volatile dwDestRegister;
	DWORD	volatile dwDMAControl;
	DWORD	volatile dwInterruptControl;


}	TMHAL_MMIO_BIU, *PTMHAL_MMIO_BIU;

typedef struct 	_TM_MMIO_AUDIO
{
	DWORD	volatile dwStatus;
	DWORD	volatile dwControl;
	DWORD	volatile dwSerial;
	DWORD	volatile dwFraming;
	DWORD	volatile dwFrequency;
	DWORD	volatile dwBase1;
	DWORD	volatile dwBase2;
	DWORD	volatile dwCount1;
	DWORD	volatile dwCount2;	
}	TMHAL_MMIO_AUDIO, *PTMHAL_MMIO_AUDIO;

typedef struct	_TMHAL_MMIO_CACHE
{
	DWORD	volatile dwDRAMBase;
	DWORD	volatile dwDRAMLimit;
	DWORD	volatile dwDRAMCacheableLimit;
	DWORD	volatile dwMemoryEventSelection;
	DWORD	volatile dwDCacheLockControl;
	DWORD	volatile dwDCacheLockLow;
	DWORD	volatile dwDCacheLockHigh;
	DWORD	volatile dwICacheParameters;
	DWORD	volatile dwMMConfiguration;
	DWORD	volatile dwArbiterBandwidthControl;
	DWORD	volatile dwPowerDown;
	DWORD	volatile dwICacheLockControl;
	DWORD	volatile dwICacheLockLow;
	DWORD	volatile dwICacheLockHigh;
	DWORD	volatile dwPLLRatios;
}	TMHAL_MMIO_CACHE, *PTMHAL_MMIO_CACHE;

#endif /* __TMMMIO_H__ */