📄 t_mmio.c
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{"CONFIG_DATA", 0x103014, 0xffffffff, 0x00000000, 0x00000000},
{"CONFIG_CTL", 0x10301c, 0x00000000, 0x00000000, 0xffffffff},
{"IO_ADR", 0x103020, 0xffffffff, 0x00000000, 0x00000000},
{"IO_DATA", 0x103024, 0xffffffff, 0x00000000, 0x00000000},
{"IO_CTL", 0x103028, 0x00000000, 0x00000000, 0xffffffff},
{"SRC_ADR", 0x10302c, 0xffffffff, 0x00000000, 0xffffffff},
{"DEST_ADR", 0x103030, 0xffffffff, 0x00000000, 0xffffffff},
{"INT_CTL", 0x103038, 0x00000000, 0x00000000, 0xffffffff},
{"DATA_IN", 0x103800, 0xffffffff, 0x00000000, 0xffffffff},
{"DATA_OUT", 0x103804, 0xffffffff, 0x00000000, 0xffffffff},
{"JTAG_CTL", 0x103808, 0x00000007, 0x00000004, 0xffffffff},
} ;
MMIO_REG mmio_reg_tm1c[] = {
{"EXCVEC", 0x100800, 0xffffffff, 0x00000000, 0x00000000},
{"ISETTING0", 0x100810, 0xffffffff, 0x00000000, 0xffffffff},
{"ISETTING1", 0x100814, 0xffffffff, 0x00000000, 0xffffffff},
{"ISETTING2", 0x100818, 0xffffffff, 0x00000000, 0xffffffff},
{"ISETTING3", 0x10081c, 0xffffffff, 0x00000000, 0xffffffff},
{"IPENDING", 0x100820, 0x00000000, 0x00000000, 0xfffffffb}, // changed TRC from ffffffff
{"ICLEAR", 0x100820, 0x00000000, 0x00000000, 0xfffffffb}, // changed TRC from ffffffff
{"IMASK", 0x100828, 0xffffffff, 0x00000000, 0xffffffff},
{"INTVEC0", 0x100880, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC1", 0x100884, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC2", 0x100888, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC3", 0x10088c, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC4", 0x100890, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC5", 0x100894, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC6", 0x100898, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC7", 0x10089c, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC8", 0x1008a0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC9", 0x1008a4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC10", 0x1008a8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC11", 0x1008ac, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC12", 0x1008b0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC13", 0x1008b4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC14", 0x1008b8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC15", 0x1008bc, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC16", 0x1008c0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC17", 0x1008c4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC18", 0x1008c8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC19", 0x1008cc, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC20", 0x1008d0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC21", 0x1008d4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC22", 0x1008d8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC23", 0x1008dc, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC24", 0x1008e0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC25", 0x1008e4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC26", 0x1008e8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC27", 0x1008ec, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC28", 0x1008f0, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC29", 0x1008f4, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC30", 0x1008f8, 0xffffffff, 0x00000000, 0x00000000},
{"INTVEC31", 0x1008fc, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER1_TMODULUS", 0x100c00, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER1_TVALUE", 0x100c04, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER1_TCTL", 0x100c08, 0x000f0f01, 0x00000000, 0xffffffff},
{"TIMER2_TMODULUS", 0x100c20, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER2_TVALUE", 0x100c24, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER2_TCTL", 0x100c28, 0x000f0f01, 0x00000000, 0xffffffff},
{"TIMER3_TMODULUS", 0x100c40, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER3_TVALUE", 0x100c44, 0xffffffff, 0x00000000, 0x00000000},
{"TIMER3_TCTL", 0x100c48, 0x000f0f01, 0x00000000, 0xffffffff},
{"SYSTIMER_TMODULUS", 0x100c60, 0xffffffff, 0x00000000, 0x00000000},
{"SYSTIMER_TVALUE", 0x100c64, 0xffffffff, 0x00000000, 0x00000000},
{"SYSTIMER_TCTL", 0x100c68, 0x000f0f01, 0x00000000, 0xffffffff},
{"BICTL", 0x101000, 0x00000101, 0x00000000, 0xffffffff},
{"BINSTLOW", 0x101004, 0xffffffff, 0x00000000, 0xffffffff},
{"BINSTHIGH", 0x101008, 0xffffffff, 0x00000000, 0xffffffff},
{"BDCTL", 0x101020, 0x0001010f, 0x00000000, 0xffffffff},
{"BDATAALOW", 0x101030, 0xffffffff, 0x00000000, 0xffffffff},
{"BDATAAHIGH", 0x101034, 0xffffffff, 0x00000000, 0xffffffff},
{"BDATAVAL", 0x101038, 0xffffffff, 0x00000000, 0xffffffff},
{"BDATAMASK", 0x10103c, 0xffffffff, 0x00000000, 0xffffffff},
{"MEM_EVENTS", 0x10000c, 0x000000ff, 0x00000000, 0xffffffff},
{"DC_LOCK_CTL", 0x100010, 0x00000001, 0x00000000, 0xffffffdf}, // changed TRC from ffffffff
{"DC_LOCK_LOW", 0x100014, 0xffffffc0, 0x00000000, 0xffffffff},
{"DC_LOCK_HIGH", 0x100018, 0xffffffc0, 0x00000000, 0xffffffff},
{"DC_PARAMS", 0x10001c, 0x00000000, 0x00404020, 0xffffffff},
{"IC_PARAMS", 0x10001c, 0x00000000, 0x00404020, 0xffffffff},
{"MM_CONFIG", 0x100100, 0x000fffff, 0x000120C4, 0xffffffff},
{"ARB_BW_CTL", 0x100104, 0x00000001, 0x00000000, 0xffffffff},
{"IC_LOCK_CTL", 0x100210, 0x00000001, 0x00000000, 0xffffffff},
{"IC_LOCK_LOW", 0x100214, 0xffffffc0, 0x00000000, 0xffffffff},
{"IC_LOCK_HIGH", 0x100218, 0xffffffc0, 0x00000000, 0xffffffff},
{"PLL_RATIOS", 0x100300, 0x00000000, 0x000000f0, 0xffffffff},
{"VI_STATUS", 0x101400, 0x00000000, 0x00000000, 0xffffffff},
{"VI_CTL", 0x101404, 0xffffffff, 0x00000000, 0x00000000},
{"VI_CLOCK", 0x101408, 0x801fffff, 0x00000000, 0x00000000},
{"VI_CAP_START", 0x10140c, 0xffffff00, 0x00000000, 0x00000000},
{"VI_CAP_SIZE", 0x101410, 0xffffff00, 0x00000000, 0x00000000},
{"VI_BASE1", 0x101414, 0xffffffc0, 0x00000000, 0x00000000},
{"VI_BASE2", 0x101418, 0xffffffc0, 0x00000000, 0x00000000},
{"VI_SIZE1", 0x10141c, 0xffffffc0, 0x00000000, 0x00000000},
{"VI_SIZE2", 0x101420, 0x00000000, 0x00000000, 0x00000000},
{"VI_Y_DELTA", 0x101424, 0x0000ffff, 0x00000000, 0x00000000},
{"BIU_STATUS", 0x103004, 0x00000000, 0x00000080, 0xffffffff},
{"BIU_CTL", 0x103008, 0x00000000, 0x00000203, 0xffffffff},
{"CONFIG_ADR", 0x103014, 0xffffffff, 0x00000000, 0x00000000},
{"CONFIG_DATA", 0x103014, 0xffffffff, 0x00000000, 0x00000000},
{"CONFIG_CTL", 0x10301c, 0x00000000, 0x00000000, 0xffffffff},
{"IO_ADR", 0x103020, 0xffffffff, 0x00000000, 0x00000000},
{"IO_DATA", 0x103024, 0xffffffff, 0x00000000, 0x00000000},
{"IO_CTL", 0x103028, 0x00000000, 0x00000000, 0xffffffff},
{"SRC_ADR", 0x10302c, 0xffffffff, 0x00000000, 0xffffffff},
{"DEST_ADR", 0x103030, 0xffffffff, 0x00000000, 0xffffffff},
{"INT_CTL", 0x103038, 0x00000000, 0x00000f00, 0xffffffff},
{"DATA_IN", 0x103800, 0xffffffff, 0x00000000, 0xffffffff},
{"DATA_OUT", 0x103804, 0xffffffff, 0x00000000, 0xffffffff},
{"JTAG_CTL", 0x103808, 0x00000007, 0x00000004, 0xffffffff},
} ;
#define MMIO_REGS_COUNT (sizeof(mmio_reg_tm1s)/sizeof(MMIO_REG))
/*
* verify_mmio
* verify a mmio register value
*/
int
verify_mmio(
int32 *mmio_virt_base,
char *name,
int32 offset,
int32 mask,
int32 exp_val
)
{
int32 obs_val ;
exp_val &= mask ;
obs_val = MMIO(offset) & mask ;
if (exp_val != obs_val)
{
printf("read error: reg %-24s addr %08x exp %08x obs %08x xor %08x\n",
name,
((char *) mmio_virt_base)+offset,
exp_val,
obs_val,
exp_val ^ obs_val) ;
obs_val = MMIO(offset) & mask ;
if (exp_val != obs_val)
{
printf("re-read error: reg %-24s addr %08x exp %08x obs %08x xor %08x\n",
name,
((char *) mmio_virt_base)+offset,
exp_val,
obs_val,
exp_val ^ obs_val) ;
}
return 1 ;
}
return 0 ;
}
/*
* setup sdram registers and verify setup
*/
int
t_mmio_sdram_setup()
{
int32 phy_sdram_base ;
int32 phy_sdram_limit ;
int errors ;
errors = 0 ;
printf("sdram limit/cacheable_limit setup\n") ;
phy_sdram_base = MMIO(DRAM_BASE) ;
printf(" physical SDRAM_VIRT_BASE: %08x\n", phy_sdram_base) ;
phy_sdram_limit = phy_sdram_base + sdram_len ;
MMIO(DRAM_LIMIT) = phy_sdram_limit ;
MMIO(DRAM_CACHEABLE_LIMIT) = phy_sdram_limit ;
errors += verify_mmio(mmio_virt_base, "DRAM_BASE",
DRAM_BASE,
0xffffffff,
phy_sdram_base) ;
errors += verify_mmio(mmio_virt_base, "DRAM_LIMIT",
DRAM_LIMIT,
0xffffffff,
phy_sdram_limit) ;
errors += verify_mmio(mmio_virt_base, "DRAM_CACHEABLE_LIMIT",
DRAM_CACHEABLE_LIMIT,
0xffffffff,
phy_sdram_limit) ;
printf(" physical SDRAM_LIMIT: %08x\n", MMIO(DRAM_LIMIT)) ;
printf(" physical SDRAM_CACHEABLE_LIMIT: %08x\n", MMIO(DRAM_CACHEABLE_LIMIT)) ;
return errors ;
}
/*
* read and display mmio registers
*/
int
t_mmio_display()
{
int32 val ;
int count ;
MMIO_REG *mmio_reg_p ;
char *mmio_virt_base_cp ;
char bfr[80] ;
mmio_virt_base_cp = (char *) mmio_virt_base ;
mmio_reg_p = GetMMIORegPtr() ;
count = MMIO_REGS_COUNT ;
while (count-- != 0)
{
val = *((uint32 *) (mmio_virt_base_cp+mmio_reg_p->offset)) ;
sprintf(bfr, "\"%s\",", mmio_reg_p->name) ;
printf("\t{%-25s 0x%06x, 0x%08x, 0x%08x},\n",
bfr,
mmio_reg_p->offset,
mmio_reg_p->rd_wr_mask,
val) ;
mmio_reg_p++ ;
}
return 0 ;
}
/*
* read and verify power on reset mmio register values
*/
int
t_mmio_read()
{
int count ;
MMIO_REG *mmio_reg_p ;
char *mmio_virt_base_cp ;
int errors ;
mmio_virt_base_cp = (char *) mmio_virt_base ;
errors = 0 ;
printf("Comparing MMIO registers with expected boot state:\n");
mmio_reg_p = GetMMIORegPtr() ;
count = MMIO_REGS_COUNT ;
while (count-- != 0)
{
errors += verify_mmio(mmio_virt_base,
mmio_reg_p->name,
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