tmhal.c

wince host 和 target PCI驱动程序

}

TMStatus	halReset (
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
        DPF(0,("tmman:halReset:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	Hal->Control->HostInterruptSpinLock = 
		halAccess32 ( HalHandle, False );

	Hal->Control->TargetInterruptSpinLock = 
		halAccess32 ( HalHandle, False );

	return statusSuccess;
}

TMStatus	halSetPeerVersion (
	UInt32	HalHandle, 
	UInt32	MajorVersion,
	UInt32	MinorVersion )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
        DPF(0,("tmman:halSetPeerVersion:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	Hal->PeerMajorVersion = MajorVersion;
	Hal->PeerMinorVersion = MinorVersion;

	return statusSuccess;
}

TMStatus	halGetPeerVersion (
	UInt32	HalHandle,
	UInt32*	MajorVersionPtr,
	UInt32*	MinorVersionPtr )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
        DPF(0,("tmman:halGetPeerVersion:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	*MajorVersionPtr = Hal->PeerMajorVersion;
	*MinorVersionPtr = Hal->PeerMinorVersion;

	return statusSuccess;
}

TMStatus	halStartDSP (
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
        DPF(0,("tmman:halStartDSP:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	if ( Hal->SpeculativeLoadFix )
	{
		/* disable the PCI apperture */
		*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL) = 
			/* read the value of DC_LOCK_CTL - retain all bits except bits 5 & 6 */
			( ( (*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL)) & (~constTMManDC_LOCK_CTL_MASK) ) | 
			/* or it with the new values of bits 5 & 6 */
			( constTMManDC_LOCK_CTL_MASK  & ( ( constTMManDC_LOCK_CTL_PDS ) << constTMManDC_LOCK_CTL_POSITION ) ) );
	}
	else
	{
		/* enable the PCI apperture */
		*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL) = 
			/* read the value of DC_LOCK_CTL - retain all bits except bits 5 & 6 */
			( ( (*(PULONG)(Hal->MMIOAddrKernel + DC_LOCK_CTL)) & (~constTMManDC_LOCK_CTL_MASK) ) | 
			/* or it with the new values of bits 5 & 6 */
			( constTMManDC_LOCK_CTL_MASK  & ( ( constTMManDC_LOCK_CTL_HEN ) << constTMManDC_LOCK_CTL_POSITION ) ) );
	}

	// clear the IMask & IClear register 
	*(PULONG)(Hal->MMIOAddrKernel + ICLEAR) = (ULONG)(~0x0);
	*(PULONG)(Hal->MMIOAddrKernel + IMASK) = (ULONG)(0x0);
	*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &= (~constTMManBIU_CTL_SR);
	*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) |= constTMManBIU_CTL_CR;

	return statusSuccess;
}

TMStatus	halStopDSP (
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;
	ULONG	Idx;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
        DPF(0,("tmman:halStopDSP:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	// biu reset BIU_CTL
	*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &= (~constTMManBIU_CTL_CR);
	*(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) |= constTMManBIU_CTL_SR;

	// reset the peripherals
	// audio out AO_CTL
	*(PULONG)( Hal->MMIOAddrKernel + AO_CTL ) = 0x80000000;
	*(PULONG)( Hal->MMIOAddrKernel + AO2_CTL ) = 0x80000000;

	// audio in AI_CTL
	*(PULONG)( Hal->MMIOAddrKernel +AI_CTL ) = 0x80000000;
	*(PULONG)( Hal->MMIOAddrKernel +AI2_CTL ) = 0x80000000;

	// video in VI_CTL
	*(PULONG)( Hal->MMIOAddrKernel +VI_CTL ) = 0x00080000;
	*(PULONG)( Hal->MMIOAddrKernel +VI2_CTL ) = 0x00080000;

	// video out VO_CTL
	*(PULONG)( Hal->MMIOAddrKernel +VO_CTL ) = 0x80000000;

	//ssi SSI_CTL
	*(PULONG)( Hal->MMIOAddrKernel +SSI_CTL ) = 0xc0000000;

	//SPDIF SDO_CTL
	*(PULONG)( Hal->MMIOAddrKernel +SPDO_CTL ) = 0x80000000;

	//IIC Slave IICS_CTL
	*(PULONG)( Hal->MMIOAddrKernel +IICS_CTL ) = 0x00200000;

	// disable 
	*(PULONG)( Hal->MMIOAddrKernel + IIC_CTL ) &= ~(0x00000001);
	//enable
	*(PULONG)( Hal->MMIOAddrKernel + IIC_CTL ) |= 0x00000001;

	// reset the VLD once
	*(PULONG)( Hal->MMIOAddrKernel + VLD_COMMAND ) = 0x00000401;

	// reset the HDVO
	*(PULONG)( Hal->MMIOAddrKernel + (HDVO_BASE + (0x20 << 1 )) ) = (ULONG)( 3 << 1 );

	*(PULONG)( Hal->MMIOAddrKernel + TP1_CTL ) = 0x80000000;
	*(PULONG)( Hal->MMIOAddrKernel + TP2_CTL ) = 0x80000000;

	//icp ICP_SR
	for ( Idx= 0 ; Idx < 10 ; Idx ++ )
	{
		// do it 10 times just to make sure ....
		if ( *( Hal->MMIOAddrKernel + ICP_SR ) & 0x01 ) 
			break;
		// changed on usman's request TRC970225
		*( Hal->MMIOAddrKernel + ICP_SR )  = 0x80;
	}

	//jtag JTAG_CTL
	*(PULONG)( Hal->MMIOAddrKernel + JTAG_DATA_IN ) = 0x00000000;
	*(PULONG)( Hal->MMIOAddrKernel + JTAG_DATA_OUT ) = 0x00000000;
	*(PULONG)( Hal->MMIOAddrKernel + JTAG_CTL ) = 0x00000004;

	return statusSuccess;

}

TMStatus	halResetDSP (
	UInt32	HalHandle )
{
	HalObject*		Hal = (HalObject*)HalHandle;
	ULONG			Idx;
	PCI_CONFIG_ADDRESS PCIConfigAddress;

	// we don't write anything into the first 3 registers
	// we write the command status at the very end.
	// write to all the registers except the last 2.
	// NT goes bonkers if we write to the interrupt register.
	for ( Idx = 3 ; Idx < (constTMMANPCIRegisters - 1)  ; Idx ++ )
	{
		if ( HalSetBusDataByOffset (
			PCIConfiguration,
			(ULONG)Hal->BusNumber,
			Hal->SlotNumber.u.AsULONG,
			&Hal->PCIRegisters[Idx], 
			(ULONG)Idx*4, 
			sizeof (ULONG) ) == 0 )
		{
			return statusPCIConfigAccessFail; 
		}
	}

	// we are breaking all NT rules by bypassing the HAL and the BIOS here
	// so don't bother doing a HalTranalateBusAddress & MmMapMmioSpace
	PCIConfigAddress.u.BitField.Zeros			= 0;
	PCIConfigAddress.u.BitField.RegisterNumber	= 0xf;
	PCIConfigAddress.u.BitField.FunctionNumber	= Hal->SlotNumber.u.bits.FunctionNumber;
	PCIConfigAddress.u.BitField.DeviceNumber		= Hal->SlotNumber.u.bits.DeviceNumber;
	PCIConfigAddress.u.BitField.BusNumber			= Hal->BusNumber;		
	PCIConfigAddress.u.BitField.Enable			= 1;

	WRITE_PORT_ULONG((PULONG)PCI_CONFIG_ADDR_PORT, PCIConfigAddress.u.Long);
	WRITE_PORT_ULONG((PULONG)PCI_CONFIG_DATA_PORT, Hal->PCIRegisters[0xf]);

	if ( HalSetBusDataByOffset (
		PCIConfiguration,
		(ULONG)Hal->BusNumber,
		Hal->SlotNumber.u.AsULONG,
		&Hal->PCIRegisters[1], 
		(ULONG)1*4, 
		sizeof (ULONG) ) == 0 )
	{
		return statusPCIConfigAccessFail; 
	}


	/* do this only if we have to run in INTEL MODE */

    // assume TM1S+
    if ( ( *(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) &
        (constTMManBIU_CTL_SE | constTMManBIU_CTL_BO | constTMManBIU_CTL_HE) ) == 0x0 )
    {	// virgin biu control
		ULONG	SwappedBIUControl;
		UCHAR	TempByte;

        SwappedBIUControl = 
            ( constTMManBIU_CTL_SE | constTMManBIU_CTL_BO | constTMManBIU_CTL_HE | constTMManBIU_CTL_SR );
        // do a dword swap
        TempByte = ((PUCHAR)&SwappedBIUControl)[0];
        ((PUCHAR)&SwappedBIUControl)[0] = ((PUCHAR)&SwappedBIUControl)[3];
        ((PUCHAR)&SwappedBIUControl)[3] = TempByte;
        TempByte = ((PUCHAR)&SwappedBIUControl)[1];
        ((PUCHAR)&SwappedBIUControl)[1] = ((PUCHAR)&SwappedBIUControl)[2];
        ((PUCHAR)&SwappedBIUControl)[2] = TempByte;

        *(PULONG)(Hal->MMIOAddrKernel + BIU_CTL) = SwappedBIUControl;

    }

    // set the cache details every time this function is called
    *(PULONG)(Hal->MMIOAddrKernel + DRAM_LIMIT) = Hal->SDRAMAddrPhysical.LowPart + Hal->SDRAMLength; 
    *(PULONG)(Hal->MMIOAddrKernel + DRAM_CACHEABLE_LIMIT) = Hal->SDRAMAddrPhysical.LowPart + Hal->SDRAMLength;

	*(PULONG)(Hal->MMIOAddrKernel + ICLEAR) = (ULONG)(~0x0);
	*(PULONG)(Hal->MMIOAddrKernel + IMASK) = (ULONG)(0x0);

}

TMStatus	halGetMMIOInfo (
	UInt32	HalHandle,
	Pointer *MMIOPhysical, 
	Pointer *MMIOKernelMapped, 
	UInt32 *MMIOSize )

{
	HalObject*	Hal = (HalObject*)HalHandle;
	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halGetMMIOInfo:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	*MMIOPhysical = (Pointer)Hal->MMIOAddrPhysical.LowPart;
	*MMIOKernelMapped = Hal->MMIOAddrKernel;
	*MMIOSize = Hal->MMIOLength;
	return statusSuccess;
}

TMStatus	halGetSDRAMInfo ( 
	UInt32	HalHandle,
	Pointer *SDRAMPhysical, 
	Pointer *SDRAMKernelMapped, 
	UInt32 *SDRAMSize )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halGetSDRAMInfo:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	*SDRAMPhysical = (Pointer)Hal->SDRAMAddrPhysical.LowPart;
	*SDRAMKernelMapped = Hal->SDRAMAddrKernel;
	*SDRAMSize = Hal->SDRAMLength;
	return statusSuccess;

}

TMStatus	halGetTMPCIInfo ( 
	UInt32	HalHandle,
	UInt32* DeviceVendorID,
	UInt32* SubsystemID,
	UInt32* ClassRevisionID )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halGetTMPCIInfo:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	*DeviceVendorID = Hal->TMDeviceVendorID;
	*SubsystemID = Hal->TMSubsystemID;
	*ClassRevisionID = Hal->TMClassRevisionID;

	return statusSuccess;
}

TMStatus	halGetBridgePCIInfo ( 
	UInt32	HalHandle,
	UInt32* DeviceVendorID,
	UInt32* SubsystemID,
	UInt32* ClassRevisionID )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halGetBridgePCIInfo:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	*DeviceVendorID = Hal->BridgeDeviceVendorID;
	*SubsystemID = Hal->BridgeSubsystemID;
	*ClassRevisionID = Hal->BridgeClassRevisionID;


	return statusSuccess;
}

TMStatus	halInstallHandler ( 
	UInt32	HalHandle,
	HalInterruptHandler Handler, 
	Pointer Context )
{
	HalObject*	Hal = (HalObject*)HalHandle;


	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halInstallHandler:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	Hal->Handler = Handler;
	Hal->Context = Context;
	return statusSuccess;
}

TMStatus	halRemoveHandler ( 
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halRemoveHandler:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	Hal->Handler = NULL;
	return statusSuccess;
}

TMStatus	halDisableInterrupts ( 
	UInt32	HalHandle,
	UInt32* Saved );

TMStatus	halRestoreInterrupts ( 
	UInt32	HalHandle,
	UInt32* Saved );

TMStatus	halDisableIRQ ( 
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;
	ULONG	InterruptControl;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halDisableIRQ:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}
	InterruptControl = *(Hal->MMIOAddrKernel + INT_CTL);

	// here SelfInterrupt indicates PCI Interrupt A
	// INT#A = 0, INT#B = 1, INT#C = 2, INT#D = 3
	// disable interrupts from the target by INT_CTL->IE off.
	InterruptControl &= ~( 0x10 << ( Hal->SelfInterrupt ) );

	*(PULONG)(Hal->MMIOAddrKernel + INT_CTL) = InterruptControl;

	return statusSuccess;
}

TMStatus	halEnableIRQ ( 
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;
	ULONG	InterruptControl;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halEnableIRQ:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}
	InterruptControl = *(Hal->MMIOAddrKernel + INT_CTL);
	InterruptControl |= ( 0x10 << ( Hal->SelfInterrupt ) );
	*(PULONG)(Hal->MMIOAddrKernel + INT_CTL) = InterruptControl;

	return statusSuccess;
}

TMStatus	halGenerateInterrupt ( 
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;
	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halGenerateInterrupt:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}
/*
	DPF(0,("tmman:halGenerateInterrupt1:IPENDING[%x]:ICLEAR[%x]:IMASK[%x]\n",
		*(PULONG)(Hal->MMIOAddrKernel + IPENDING),
		*(PULONG)(Hal->MMIOAddrKernel + ICLEAR),
		*(PULONG)(Hal->MMIOAddrKernel + IMASK ) ));	
*/
	*(PULONG)(Hal->MMIOAddrKernel + IPENDING) = ( 1<< Hal->PeerInterrupt ); 
/*
	DPF(0,("tmman:halGenerateInterrupt2:IPENDING[%x]:ICLEAR[%x]:IMASK[%x]\n",
		*(PULONG)(Hal->MMIOAddrKernel + IPENDING),
		*(PULONG)(Hal->MMIOAddrKernel + ICLEAR),
		*(PULONG)(Hal->MMIOAddrKernel + IMASK ) ));	
*/
	return statusSuccess;
}

TMStatus	halAcknowledgeInterrupt (
	UInt32	HalHandle )
{
	HalObject*	Hal = (HalObject*)HalHandle;
	ULONG	InterruptControl;

	if ( objectValidate ( Hal, HalFourCC ) != True )
	{
		DPF(0,("tmman:halAcknowledgeInterrupt:objectValidate:FAIL\n" ));
		return statusInvalidHandle;
	}

	/* FOR TM1 */
	/*
		reset	MMIO->dwInterruptControl:INT(3..0)
		reset	MMIO->dwInterruptControl:IE(7..4)
	*/
	while ( 1 )
	{
		if ( halAccess32 ( HalHandle, 
			Hal->Control->TargetInterruptSpinLock  ) == False )
		{
			Hal->Control->HostInterruptSpinLock = 
				halAccess32 ( HalHandle, True  );

			if ( halAccess32 ( HalHandle, 
				Hal->Control->TargetInterruptSpinLock  ) == True )
			{
				Hal->Control->HostInterruptSpinLock = 
					halAccess32 ( HalHandle, False  );			
			}
			else
			{
				InterruptControl = *(Hal->MMIOAddrKernel + INT_CTL);

				// here SelfInterrupt indicates PCI Interrupt A
				// INT#A = 0, INT#B = 1, INT#C = 2, INT#D = 3
				InterruptControl &=
					( ~( 1 << ( Hal->SelfInterrupt ) )  &
					~( 0x10 << ( Hal->SelfInterrupt ) ) );

				*(PULONG)(Hal->MMIOAddrKernel + INT_CTL) = InterruptControl;

				Hal->Control->HostInterruptSpinLock = 
					halAccess32 ( HalHandle, False  );
				break;
			}

		}