📄 ln97xend.h
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/* ln97xEnd.h - END based AMD LANCE Ethernet header */
/*
modification history
--------------------
01a,07dec98,snk added support 7997x[012] across architectures.
written from 01b of lnPciEnd.h
*/
#ifndef __INCln97xEndh
#define __INCln97xEndh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include "end.h"
#include "cacheLib.h"
#if FALSE
#define DRV_DEBUG /* temporary should be taken out */
#endif
/**********************************************/
/* define the various levels of debugging if the DRV_DEBUG is defined */
#ifdef DRV_DEBUG
#include "logLib.h"
#define DRV_DEBUG_OFF 0x0000
#define DRV_DEBUG_RX 0x0001
#define DRV_DEBUG_TX 0x0002
#define DRV_DEBUG_INT 0x0004
#define DRV_DEBUG_POLL (DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
#define DRV_DEBUG_POLL_RX 0x0008
#define DRV_DEBUG_POLL_TX 0x0010
#define DRV_DEBUG_LOAD 0x0020
#define DRV_DEBUG_LOAD2 0x0040
#define DRV_DEBUG_IOCTL 0x0080
#define DRV_DEBUG_RESET 0x0100
#define DRV_DEBUG_MCAST 0x0200
#define DRV_DEBUG_CSR 0x0400
#define DRV_DEBUG_RX_PKT 0x0800
#define DRV_DEBUG_POLL_REDIR 0x10000
#define DRV_DEBUG_LOG_NVRAM 0x20000
#define DRV_DEBUG_ALL 0xfffff
#endif /* DRV_DEBUG */
/* device IO or memory mapped accessa and data registers */
#define LN_97X_RDP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x10))
#define LN_97X_RAP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x14))
#define LN_97X_RST ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x18))
#define LN_97X_BDP ((UINT32 *)((UINT32)(pDrvCtrl->devAdrs) + 0x1C))
/* csr and bcr addresses */
#define CSR(x) (x)
#define BCR(x) (x)
#define BCR2_LEDPE 0x1000 /* LED programing enable */
/****************************************************/
/* Definitions for fields and bits in the LN_DEVICE */
#define CSR0_ERR 0x8000 /* (RO) err flg (BABL|CERR|MISS|MERR) */
#define CSR0_BABL 0x4000 /* (RC) babble transmitter timeout */
#define CSR0_CERR 0x2000 /* (RC) collision error */
#define CSR0_MISS 0x1000 /* (RC) missed packet */
#define CSR0_MERR 0x0800 /* (RC) memory error */
#define CSR0_RINT 0x0400 /* (RC) receiver interrupt */
#define CSR0_TINT 0x0200 /* (RC) transmitter interrupt */
#define CSR0_IDON 0x0100 /* (RC) initialization done */
#define CSR0_INTR 0x0080 /* (RO) interrupt flag */
#define CSR0_INEA 0x0040 /* (RW) interrupt enable */
#define CSR0_RXON 0x0020 /* (RO) receiver on */
#define CSR0_TXON 0x0010 /* (RO) transmitter on */
#define CSR0_TDMD 0x0008 /* (WOO)transmit demand */
#define CSR0_STOP 0x0004 /* (WOO)stop (& reset) chip */
#define CSR0_STRT 0x0002 /* (RW) start chip */
#define CSR0_INIT 0x0001 /* (RW) initialize (acces init block) */
#define CSR0_INTMASK (CSR0_BABL | CSR0_CERR | CSR0_MISS | \
CSR0_MERR | CSR0_RINT | CSR0_TINT | \
CSR0_IDON | CSR0_INEA)
#define CSR3_BSWP 0x0004 /* Byte Swap */
/* BCR 2 */
#define BCR2_AUTO_SELECT 0x0002 /* auto select port type 10BT/AUI */
#define BCR2_LEDPE 0x1000 /* LED programing enable */
/* BCR 9 */
#define BCR9_FDEN 0x0001 /* Full Duplex Enable */
/* CSR 15 */
#define CSR15_DRX 0x0001 /* Disable Receiver */
#define CSR15_DTX 0x0002 /* Disable Transmitter */
#define CSR15_LOOP 0x0004 /* Loopback(external) */
#define CSR15_INTL 0x0040 /* Loopback(internal) */
/* BCR 18 */
#define BCR18_NOUFLO 0x0800 /* No Underflow on Transmit */
#define BCR18_MEMCMD 0x0200 /* Memory read multiple */
#define BCR18_BREADE 0x0040 /* Burst Read Enable*/
#define BCR18_BWRITE 0x0020 /* Burst Write Enable */
/* BCR 32 */
#define BCR32_DANAS 0x0080 /* Disable Auto-Negotiation Setup*/
#define BCR32_PHYRST 0x0040 /*PHY reset*/
#define BCR32_XPHYANE 0x0020 /* PHY Auto-Negotiation Enable */
#define BCR32_XPHYFD 0x0010 /* PHY Full Duplex */
#define BCR32_XPHYSP 0x0008 /* PHY Speed: '1' - 100M; '0' - 10M */
#define BCR32_MIILP 0x0002 /* MII LoopBack*/
/* Don't set XPHYSP or XPHYFD when XPHYANE is set */
#define BCR2_AUTO_SELECT 0x0002 /* auto select port type 10BT/AUI */
/* BCR 20 software style register */
#define BCR20_SSIZE32 0x0100
#define BCR20_SWSTYLE_LANCE 0x0000
#define BCR20_SWSTYLE_ILACC 0x0001
#define BCR20_SWSTYLE_PCNET 0x0002
/* Control block definitions for AMD LANCE (Ethernet) chip. */
typedef struct
{
ULONG rdp; /* register data Port */
ULONG rap; /* Register Address Port */
ULONG rst; /* Reset Register */
ULONG bdp; /* Bus Configuration Register Data Port */
} LN_DEVICE;
/* Initialization Block */
typedef struct lnIB
{
ULONG lnIBMode; /* mode register */
UCHAR lnIBPadr [8]; /* PADR: bswapd ethnt phys address */
UCHAR lnIBLadrf [8]; /* logical address filter */
ULONG lnIBRdra; /* RDRA: read ring address, long word */
ULONG lnIBTdra; /* TDRA: transmit ring address long word */
} LN_IB;
/* Receive Message Descriptor Entry.*/
typedef struct lnRMD
{
ULONG lnRMD0; /* bits 31:00 of receive buffer address */
ULONG lnRMD1; /* status & buffer byte count (negative) */
ULONG lnRMD2; /* message byte count */
ULONG lnRMD3; /* reserved */
} LN_RMD;
/* Transmit Message Descriptor Entry. */
typedef struct lnTMD
{
ULONG lnTMD0; /* bits 31:00 of transmit buffer address */
ULONG lnTMD1; /* message byte count */
ULONG lnTMD2; /* errors */
ULONG lnTMD3; /* reserved */
} LN_TMD;
/* initialization block */
#define IB_MODE_TLEN_MSK 0xf0000000
#define IB_MODE_RLEN_MSK 0x00f00000
/* receive descriptor */
#define RMD1_OWN 0x80000000 /* Own */
#define RMD1_ERR 0x40000000 /* Error */
#define RMD1_FRAM 0x20000000 /* Framming Error */
#define RMD1_OFLO 0x10000000 /* Overflow */
#define RMD1_CRC 0x08000000 /* CRC */
#define RMD1_BUFF 0x04000000 /* Buffer Error */
#define RMD1_STP 0x02000000 /* Start of Packet */
#define RMD1_ENP 0x01000000 /* End of Packet */
#define RMD1_RES 0x00ff0000 /* reserved */
#define RMD1_CNST 0x0000f000 /* rmd1 constant value */
#define RMD1_BCNT_MSK 0x00000fff /* buffer cnt mask */
#define RMD2_MCNT_MSK 0x00000fff /* message buffer cnt mask */
/* transmit descriptor */
#define TMD1_OWN 0x80000000 /* Own */
#define TMD1_ERR 0x40000000 /* Error */
#define TMD1_MORE 0x10000000 /* More than One Retry */
#define TMD1_ONE 0x08000000 /* One Retry */
#define TMD1_DEF 0x04000000 /* Deferred */
#define TMD1_STP 0x02000000 /* Start of Packet */
#define TMD1_ENP 0x01000000 /* End of Packet */
#define TMD1_RES 0x00FF0000 /* High Address */
#define TMD1_CNST 0x0000f000 /* tmd1 constant value */
#define TMD2_BUFF 0x80000000 /* Buffer Error */
#define TMD2_UFLO 0x40000000 /* Underflow Error */
#define TMD2_LCOL 0x10000000 /* Late Collision */
#define TMD2_LCAR 0x08000000 /* Lost Carrier */
#define TMD2_RTRY 0x04000000 /* Retry Error */
#define TMD2_TDR 0x03FF0000 /* Time Domain Reflectometry */
#define TMD1_BCNT_MSK 0x00000fff /* buffer cnt mask */
#define rBufAddr lnRMD0
#define rBufRmd1 lnRMD1
#define rBufMskCnt lnRMD2
#define rBufRmd3 lnRMD3
#define tBufAddr lnTMD0
#define tBufTmd1 lnTMD1
#define tBufTmd2 lnTMD2
#define tBufTmd3 lnTMD3
/* CRC for logical address filter */
#define LN_CRC_POLYNOMIAL 0xedb88320 /* CRC polynomial */
#define LN_CRC_TO_LAF_IX(crc) ((crc) >> 26) /* get 6 MSBits */
#define LN_LAF_LEN 8 /* logical addr filter legth */
#define LN_LA_LEN 6 /* logical address length */
/* Definitions for the drvCtrl specific flags field */
#define LS_PROMISCUOUS_FLAG 0x1 /* set the promiscuous mode */
#define LS_MEM_ALLOC_FLAG 0x2 /* allocating memory flag */
#define LS_PAD_USED_FLAG 0x4 /* padding used flag */
#define LS_RCV_HANDLING_FLAG 0x8 /* handling recv packet */
#define LS_START_OUTPUT_FLAG 0x10 /* trigger output flag */
#define LS_POLLING 0x20 /* polling flag */
#define LS_MODE_MEM_IO_MAP 0x100 /* device registers memory mapped */
#define LS_MODE_DWIO 0x200 /* device in 32 bit mode */
/* descriptor size */
#define RMD_SIZ sizeof(LN_RMD)
#define TMD_SIZ sizeof(LN_TMD)
#define IB_SIZ sizeof(LN_IB)
/* free routine hooked to the transmit descriptor */
typedef struct freeArgs
{
void * arg1;
void * arg2;
} FREE_ARGS;
/* The definition of the driver control structure */
typedef struct ln97xDevice
{
END_OBJ endObj; /* The class we inherit from */
LN_IB * ib; /* ptr to Initialization Block */
int unit; /* unit number of the device */
int rmdIndex; /* current RMD index */
int rringSize; /* RMD ring size */
int rringLen; /* RMD ring length (bytes) */
LN_RMD * pRring; /* RMD ring start */
int tmdIndex; /* current TMD index */
int tmdIndexC; /* current TMD index */
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