s3c2410.h

武汉创维特公司的2410arm9开发办的can linux源代码

#define TCNTO1			bPWM_BUFn(1,0x8)
#define TCNTB2			bPWM_BUFn(2,0x0)
#define TCMPB2			bPWM_BUFn(2,0x4)
#define TCNTO2			bPWM_BUFn(2,0x8)
#define TCNTB3			bPWM_BUFn(3,0x0)
#define TCMPB3			bPWM_BUFn(3,0x4)
#define TCNTO3			bPWM_BUFn(3,0x8)
#define TCNTB4			bPWM_BUFn(4,0x0)
#define TCNTO4			bPWM_BUFn(4,0x4)
/* Fields */
#define fTCFG0_DZONE		Fld(8,16)	/* the dead zone length (= timer 0) */
#define fTCFG0_PRE1		Fld(8,8)	/* prescaler value for time 2,3,4 */
#define fTCFG0_PRE0		Fld(8,0)        /* prescaler value for time 0,1 */
#define fTCON_TIMER0	Fld(5,0)
#define fTCON_TIMER1	Fld(4,8)
#define fTCON_TIMER2	Fld(4,12)
#define fTCON_TIMER3	Fld(4,16)

/* bits */
#define TCFG0_DZONE(x)		FInsrt((x), fTCFG0_DZONE)
#define TCFG0_PRE1(x)		FInsrt((x), fTCFG0_PRE1)
#define TCFG0_PRE0(x)		FInsrt((x), fTCFG0_PRE0)

#define TCON_4_AUTO		(1 << 22)	/* auto reload on/off for Timer 4 */
#define TCON_4_UPDATE		(1 << 21)	/* manual Update TCNTB4 */
#define TCON_4_ONOFF		(1 << 20)	/* 0: Stop, 1: start Timer 4 */
#define COUNT_4_ON		(TCON_4_ONOFF*1)
#define COUNT_4_OFF		(TCON_4_ONOFF*0)
#define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
#define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
#define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
#define TCON_2_AUTO     (1 << 15)       /* auto reload on/off for Timer 3 */
#define TCON_2_INVERT   (1 << 14)       /* 1: Inverter on for TOUT3 */
#define TCON_2_MAN      (1 << 13)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_2_ONOFF    (1 << 12)       /* 0: Stop, 1: start Timer 3 */
#define TCON_1_AUTO     (1 << 11)       /* auto reload on/off for Timer 3 */
#define TCON_1_INVERT   (1 << 10)       /* 1: Inverter on for TOUT3 */
#define TCON_1_MAN      (1 << 9)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_1_ONOFF    (1 << 8)       /* 0: Stop, 1: start Timer 3 */
#define TCON_0_AUTO     (1 << 3)       /* auto reload on/off for Timer 3 */
#define TCON_0_INVERT   (1 << 2)       /* 1: Inverter on for TOUT3 */
#define TCON_0_MAN      (1 << 1)       /* manual Update TCNTB3,TCMPB3 */
#define TCON_0_ONOFF    (1 << 0)       /* 0: Stop, 1: start Timer 3 */

#define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
#define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
#define TIMER3_IVT_ON   (TCON_3_INVERT*1)
#define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
#define TIMER3_MANUP    (TCON_3_MAN*1)
#define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
#define TIMER3_ON       (TCON_3_ONOFF*1)
#define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
#define TIMER2_ATLOAD_ON        (TCON_2_AUTO*1)
#define TIMER2_ATLAOD_OFF       FClrBit(TCON, TCON_2_AUTO)
#define TIMER2_IVT_ON   (TCON_2_INVERT*1)
#define TIMER2_IVT_OFF  (FClrBit(TCON, TCON_2_INVERT))
#define TIMER2_MANUP    (TCON_2_MAN*1)
#define TIMER2_NOP      (FClrBit(TCON, TCON_2_MAN))
#define TIMER2_ON       (TCON_2_ONOFF*1)
#define TIMER2_OFF      (FClrBit(TCON, TCON_2_ONOFF))
#define TIMER1_ATLOAD_ON        (TCON_1_AUTO*1)
#define TIMER1_ATLAOD_OFF       FClrBit(TCON, TCON_1_AUTO)
#define TIMER1_IVT_ON   (TCON_1_INVERT*1)
#define TIMER1_IVT_OFF  (FClrBit(TCON, TCON_1_INVERT))
#define TIMER1_MANUP    (TCON_1_MAN*1)
#define TIMER1_NOP      (FClrBit(TCON, TCON_1_MAN))
#define TIMER1_ON       (TCON_1_ONOFF*1)
#define TIMER1_OFF      (FClrBit(TCON, TCON_1_ONOFF))
#define TIMER0_ATLOAD_ON        (TCON_0_AUTO*1)
#define TIMER0_ATLAOD_OFF       FClrBit(TCON, TCON_0_AUTO)
#define TIMER0_IVT_ON   (TCON_0_INVERT*1)
#define TIMER0_IVT_OFF  (FClrBit(TCON, TCON_0_INVERT))
#define TIMER0_MANUP    (TCON_0_MAN*1)
#define TIMER0_NOP      (FClrBit(TCON, TCON_0_MAN))
#define TIMER0_ON       (TCON_0_ONOFF*1)
#define TIMER0_OFF      (FClrBit(TCON, TCON_0_ONOFF))

#define TCON_TIMER1_CLR   FClrFld(TCON, fTCON_TIMER1);
#define TCON_TIMER2_CLR   FClrFld(TCON, fTCON_TIMER2);
#define TCON_TIMER3_CLR   FClrFld(TCON, fTCON_TIMER3);


/*
 * LCD Controller (Page 15-23)
 *
 * Register
   LCDCON1	LCD Control 1				[word, R/W, 0x00000000]
   LCDCON2	LCD Control 2				[word, R/W, 0x00000000]
   LCDCON3	LCD Control 3				[word, R/W, 0x00000000]
   LCDCON4	LCD Control 4				[word, R/W, 0x00000000]
   LCDCON5	LCD Control 5				[word, R/W, 0x00000000]
   LCDADDR1	STN/TFT: Frame Buffer Start Addr1	[word, R/W, 0x00000000]
   LCDADDR2	STN/TFT: Frame Buffer Start Addr2	[word, R/W, 0x00000000]
   LCDADDR3	STN/TFT: Virtual Screen Address Set	[word, R/W, 0x00000000]
   REDLUT	STN: Red Lookup Table			[word, R/W, 0x00000000]
   GREENLUT	STN: Green Lookup Table			[word, R/W, 0x00000000]
   BLUELUT	STN: Blue Lookup Table			[word, R/W, 0x0000]
   DP1_2	STN: Dithering Pattern Duty 1/2		[word, R/W]
   DP4_7	STN: Dithering Pattern Duty 4/7		[word, R/W]
   DP3_5	STN: Dithering Pattern Duty 3/5		[word, R/W]
   DP2_3	STN: Dithering Pattern Duty 2/3		[word, R/W]
   DP5_7	STN: Dithering Pattern Duty 5/7		[word, R/W]
   DP3_4	STN: Dithering Pattern Duty 3/4		[word, R/W]
   DP4_5	STN: Dithering Pattern Duty 4/5		[word, R/W]
   DP6_7	STN: Dithering Pattern Duty 6/7		[word, R/W]
   DITHMODE	STN: Dithering Mode			[word, R/W, 0x00000000]
   TPAL		TFT: Temporary Pallete			[word, R/W, 0x00000000]
 *
 */

#define bLCD_CTL(Nb)	__REG(0x4d000000 + (Nb))
#define LCDCON1		bLCD_CTL(0x00)
#define LCDCON2		bLCD_CTL(0x04)
#define LCDCON3		bLCD_CTL(0x08)
#define LCDCON4		bLCD_CTL(0x0c)
#define LCDCON5		bLCD_CTL(0x10)
#define LCDADDR1	bLCD_CTL(0x14)
#define LCDADDR2	bLCD_CTL(0x18)
#define LCDADDR3	bLCD_CTL(0x1c)
#define REDLUT		bLCD_CTL(0x20)
#define GREENLUT	bLCD_CTL(0x24)
#define BLUELUT		bLCD_CTL(0x28)
#define DITHMODE	bLCD_CTL(0x4c)
#define TPAL		bLCD_CTL(0x50)
#define LCDINTPND	bLCD_CTL(0x54)
#define LCDSRCPND	bLCD_CTL(0x58)
#define LCDINTMSK	bLCD_CTL(0x5c)
#define LCDLPCSEL	bLCD_CTL(0x60)

#define fLCD1_LINECNT	Fld(10,18)	/* the status of the line counter */
#define LCD1_LINECNT	FMsk(fLCD_LINECNT)

#define fLCD1_CLKVAL	Fld(10,8)	/* rates of VCLK and CLKVAL[9:0] */
#define LCD1_CLKVAL(x)	FInsrt((x), fLCD1_CLKVAL)
#define LCD1_CLKVAL_MSK	FMask(fLCD1_CLKVAL)

#define LCD1_MMODE (1<<7)

#define fLCD1_PNR	Fld(2,5)	/* select the display mode */
#define LCD1_PNR_4D	FInsrt(0x0, fLCD1_PNR)	/* STN: 4-bit dual scan */
#define LCD1_PNR_4S	FInsrt(0x1, fLCD1_PNR)	/* STN: 4-bit single scan */
#define LCD1_PNR_8S	FInsrt(0x2, fLCD1_PNR)	/* STN: 8-bit single scan */
#define LCD1_PNR_TFT	FInsrt(0x3, fLCD1_PNR)	/* TFT LCD */

#define fLCD1_BPP	Fld(4,1)	/* select BPP(Bit Per Pixel) */
#define LCD1_BPP_1S	FInsrt(0x0, fLCD1_BPP)	/* STN: 1 bpp, mono */
#define LCD1_BPP_2S	FInsrt(0x1, fLCD1_BPP)	/* STN: 2 bpp, 4-grey */
#define LCD1_BPP_4S	FInsrt(0x2, fLCD1_BPP)	/* STN: 4 bpp, 16-grey */
#define LCD1_BPP_8S	FInsrt(0x3, fLCD1_BPP)	/* STN: 8 bpp, color */
#define LCD1_BPP_12S	FInsrt(0x4, fLCD1_BPP)	/* STN: 12 bpp, color */
#define LCD1_BPP_1T	FInsrt(0x8, fLCD1_BPP)	/* TFT: 1 bpp */
#define LCD1_BPP_2T	FInsrt(0x9, fLCD1_BPP)	/* TFT: 2 bpp */
#define LCD1_BPP_4T	FInsrt(0xa, fLCD1_BPP)	/* TFT: 4 bpp */
#define LCD1_BPP_8T	FInsrt(0xb, fLCD1_BPP)	/* TFT: 8 bpp */
#define LCD1_BPP_16T	FInsrt(0xc, fLCD1_BPP)	/* TFT: 16 bpp */

#define LCD1_ENVID	(1 << 0)	/* 1: Enable the video output */

#define fLCD2_VBPD	Fld(8,24)	/* TFT: (Vertical Back Porch)
	   # of inactive lines at the start of a frame,
	   after vertical synchronization period. */
//#define LCD2_VBPD	FMsk(fLCD2_VBPD)
#define LCD2_VBPD(x)	FInsrt((x), fLCD2_VBPD)

#define fLCD2_LINEVAL	Fld(10,14)	/* TFT/STN: vertical size of LCD */
#define LCD2_LINEVAL(x)	FInsrt((x), fLCD2_LINEVAL)
#define LCD2_LINEVAL_MSK	FMsk(fLCD2_LINEVAL)

#define fLCD2_VFPD	Fld(8,6)	/* TFT: (Vertical Front Porch)
	   # of inactive lines at the end of a frame,
	   before vertical synchronization period. */
//#define LCD2_VFPD	FMsk(fLCD2_VFPD)
#define LCD2_VFPD(x)	FInsrt((x), fLCD2_VFPD)

#define fLCD2_VSPW	Fld(6,0)	/* TFT: (Vertical Sync Pulse Width)
	   the VSYNC pulse's high level width
	   by counting the # of inactive lines */
//#define LCD2_VSPW	FMsk(fLCD2_VSPW)
#define LCD2_VSPW(x)	FInsrt((x), fLCD2_VSPW)

#define fLCD3_HBPD	Fld(7,19)	/* TFT: (Horizontal Back Porch)
	   # of VCLK periods between the falling edge of HSYNC
	   and the start of active data */
//#define LCD3_HBPD	FMsk(fLCD3_HBPD)
#define LCD3_HBPD(x)	FInsrt((x), fLCD3_HBPD)

#define fLCD3_WDLY	Fld(7,19)	/* STN: delay between VLINE and
	   VCLK by counting the # of the HCLK */
#define LCD3_WDLY	FMsk(fLCD3_WDLY)
#define LCD3_WDLY	FMsk(fLCD3_WDLY)
#define LCD3_WDLY_16	FInsrt(0x0, fLCD3_WDLY)	/* 16 clock */
#define LCD3_WDLY_32	FInsrt(0x1, fLCD3_WDLY)	/* 32 clock */
#define LCD3_WDLY_64	FInsrt(0x2, fLCD3_WDLY)	/* 64 clock */
#define LCD3_WDLY_128	FInsrt(0x3, fLCD3_WDLY)	/* 128 clock */

#define fLCD3_HOZVAL	Fld(11,8)	/* horizontal size of LCD */
//#define LCD3_HOZVAL	FMsk(fLCD3_HOZVAL)
#define LCD3_HOZVAL(x)	FInsrt((x), fLCD3_HOZVAL)
#define LCD3_HOZVAL_MSK	FMsk(fLCD3_HOZVAL)

#define fLCD3_HFPD	Fld(8,0)	/* TFT: (Horizontal Front Porch)
	   # of VCLK periods between the end of active date
	   and the rising edge of HSYNC */
//#define LCD3_HFPD	FMsk(LCD3_HFPD)
#define LCD3_HFPD(x)	FInsrt((x), fLCD3_HFPD)

#define fLCD3_LINEBLNK	Fld(8,0)	/* STN: the blank time
	   in one horizontal line duration time.
	   the unit of LINEBLNK is HCLK x 8 */
//#define LCD3_LINEBLNK	FMsk(fLCD3_LINEBLNK)
#define LCD3_LINEBLNK	FInsrt(fLCD3_LINEBLNK)

#if 0
#define LCD4_PALADDEN	(1 << 24)	/* TFT: enable Pallete index offset */

#define fLCD4_ADDVAL	Fld(8,16)	/* TFT: Pallete index offset */
#define LCD4_ADDVAL	FMsk(fLCD4_ADDVAL)
#endif

#define fLCD4_MVAL	Fld(8,8)	/* STN: the rate at which the VM signal
	   will toggle if the MMODE bit is set logic '1' */
//#define LCD4_MVAL	FMsk(fLCD4_MVAL)
#define LCD4_MVAL(x)	FInsrt((x), fLCD4_MVAL)

#define fLCD4_HSPW	Fld(8,0)	/* TFT: (Horizontal Sync Pulse Width)
	   HSYNC pulse's high lvel width by counting the # of the VCLK */
//#define LCD4_HSPW	FMsk(fLCD4_HSPW)
#define LCD4_HSPW(x)	FInsrt((x), fLCD4_HSPW)

#define fLCD4_WLH	Fld(8,0)	/* STN: VLINE pulse's high level width
	   by counting the # of the HCLK */
//#define LCD4_WLH	FMsk(fLCD4_WLH)
#define LCD4_WLH(x)	FInsrt((x), fLCD4_WLH)
#define LCD4_WLH_16	FInsrt(0x0, fLCD4_WLH)	/* 16 clock */
#define LCD4_WLH_32	FInsrt(0x1, fLCD4_WLH)	/* 32 clock */
#define LCD4_WLH_64	FInsrt(0x2, fLCD4_WLH)	/* 64 clock */
#define LCD4_WLH_128	FInsrt(0x3, fLCD4_WLH)	/* 128 clock */

#define fLCD5_VSTAT	Fld(2,19)	/* TFT: Vertical Status (ReadOnly) */
#define LCD5_VSTAT	FMsk(fLCD5_VSTAT)
#define LCD5_VSTAT_VS	0x00	/* VSYNC */
#define LCD5_VSTAT_BP	0x01	/* Back Porch */
#define LCD5_VSTAT_AC	0x02	/* Active */
#define LCD5_VSTAT_FP	0x03	/* Front Porch */

#define fLCD5_HSTAT	Fld(2,17)	/* TFT: Horizontal Status (ReadOnly) */
#define LCD5_HSTAT	FMsk(fLCD5_HSTAT)
#define LCD5_HSTAT_HS	0x00	/* HSYNC */
#define LCD5_HSTAT_BP	0x01	/* Back Porch */
#define LCD5_HSTAT_AC	0x02	/* Active */
#define LCD5_HSTAT_FP	0x03	/* Front Porch */

#if 0
#define LCD5_BGREN	(1 << 16)	/* STN,1 : VD output order is BGR */
#define LCD5_SLOWCLK	(1 << 14)	/* STN,1 : SLOW CLK SYNC enable */
#define LCD5_SELFREF	(1 << 13)	/* STN,1 : LCD self refresh enable */
#endif
#define LCD5_BPP24BL	(1 << 12)
#define LCD5_FRM565		(1 << 11)
#define LCD5_INVVCLK	(1 << 10)	/* STN/TFT :
	   1 : video data is fetched at VCLK falling edge
	   0 : video data is fetched at VCLK rising edge */
#define LCD5_INVVLINE	(1 << 9)	/* STN/TFT :
	   1 : VLINE/HSYNC pulse polarity is inverted */
#define LCD5_INVVFRAME	(1 << 8)	/* STN/TFT :
	   1 : VFRAME/VSYNC pulse polarity is inverted */
#define LCD5_INVVD	(1 << 7)	/* STN/TFT :
	   1 : VD (video data) pulse polarity is inverted */
#define LCD5_INVVDEN	(1 << 6)	/* TFT :
	   1 : VDEN signal polarity is inverted */
#define LCD5_INVPWREN	(1 << 5)
#define LCD5_INVLEND	(1 << 4)	/* TFT :
	   1 : LEND signal polarity is inverted */
#define LCD5_PWREN	(1 << 3)
#define LCD5_LEND	(1 << 2)	/* TFT,1 : Enable LEND signal */
#define LCD5_BSWP	(1 << 1)	/* STN/TFT,1 : Byte swap enable */
#define LCD5_HWSWP	(1 << 0)	/* STN/TFT,1 : HalfWord swap enable */

#define fLCDADDR_BANK	Fld(9,21)	/* bank location for video buffer */
#define LCDADDR_BANK(x)	FInsrt((x), fLCDADDR_BANK)

#define fLCDADDR_BASEU	Fld(21,0)	/* address of upper left corner */
#define LCDADDR_BASEU(x)	FInsrt((x), fLCDADDR_BASEU)

#define fLCDADDR_BASEL	Fld(21,0)	/* address of lower right corner */
#define LCDADDR_BASEL(x)	FInsrt((x), fLCDADDR_BASEL)

#define fLCDADDR_OFFSET	Fld(11,11)	/* Virtual screen offset size
					   (# of half words) */
#define LCDADDR_OFFSET(x)	FInsrt((x), fLCDADDR_OFFSET)

#define fLCDADDR_PAGE	Fld(11,0)	/* Virtual screen page width
					   (# of half words) */
#define LCDADDR_PAGE(x)	FInsrt((x), fLCDADDR_PAGE)

#define TPAL_LEN	(1 << 24)	/* 1 : Temp. Pallete Register enable */
#define fTPAL_VAL	Fld(24,0)	/* Temp. Pallete Register value */
//#define TPAL_VAL	FMsk(fTPAL_VAL)
#define TPAL_VAL(x)	FInsrt((x), fTPAL_VAL)
#define TPAL_VAL_RED(x)	FInsrt((x), Fld(8,16))
#define TPAL_VAL_GREEN(x)	FInsrt((x), Fld(8,8))
#define TPAL_VAL_BLUE(x)	FInsrt((x), Fld(8,0))


/*
 * NAND Flash Controller (Page 6-1 ~ 6-8)
 *
 * Register
   NFCONF   NAND Flash Configuration    [word, R/W, 0x00000000]
   NFCMD    NAND Flash Command Set      [word, R/W, 0x00000000]
   NFADDR   NAND Flash Address Set      [word, R/W, 0x00000000]
   NFDATA   NAND Flash Data             [word, R/W, 0x00000000]
   NFSTAT   NAND Flash Status           [word, R, 0x00000000]
   NFECC    NAND Flash ECC              [3 bytes, R, 0x00000000]
 *
 */
#define bNAND_CTL(Nb)	__REG(0x4e000000 + (Nb))