s3c2410.h

武汉创维特公司的2410arm9开发办的can linux源代码

#define GPIO_MODE_SDCLK			GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDO		GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDI		GPIO_MODE_ALT0
#define GPIO_MODE_CDCLK			GPIO_MODE_ALT0
#define GPIO_MODE_I2SSCLK		GPIO_MODE_ALT0
#define GPIO_MODE_I2SLRCK		GPIO_MODE_ALT0
#define GPIO_MODE_I2SSDI_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_nSS			GPIO_MODE_ALT1
#define GPIO_MODE_EINT			GPIO_MODE_ALT0
#define GPIO_MODE_nYPON			GPIO_MODE_ALT1
#define GPIO_MODE_YMON			GPIO_MODE_ALT1
#define GPIO_MODE_nXPON			GPIO_MODE_ALT1
#define GPIO_MODE_XMON			GPIO_MODE_ALT1
#define GPIO_MODE_UART			GPIO_MODE_ALT0	
#define GPIO_MODE_TCLK_ABNORMAL		GPIO_MODE_ALT1
#define GPIO_MODE_SPICLK_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_SPIMOSI_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_SPIMISO_ABNORMAL	GPIO_MODE_ALT1
#define GPIO_MODE_LCD_PWRDN		GPIO_MODE_ALT1

/* UART */
#define UART_CTL_BASE		0x50000000
#define UART0_CTL_BASE		UART_CTL_BASE
#define UART1_CTL_BASE		UART_CTL_BASE + 0x4000
#define UART2_CTL_BASE		UART_CTL_BASE + 0x8000
#define bUART(x, Nb)		__REG(UART_CTL_BASE + (x)*0x4000 + (Nb))
/* Offset */
#define oULCON			0x00	/* R/W, UART line control register */
#define oUCON			0x04	/* R/W, UART control register */
#define oUFCON			0x08	/* R/W, UART FIFO control register */
#define oUMCON			0x0C	/* R/W, UART modem control register */
#define oUTRSTAT		0x10	/* R  , UART Tx/Rx status register */
#define oUERSTAT		0x14	/* R  , UART Rx error status register */
#define oUFSTAT			0x18	/* R  , UART FIFO status register */
#define oUMSTAT			0x1C	/* R  , UART Modem status register */
#define oUTXHL			0x20	/*   W, UART transmit(little-end) buffer */
#define oUTXHB			0x23	/*   W, UART transmit(big-end) buffer */
#define oURXHL			0x24	/* R  , UART receive(little-end) buffer */
#define oURXHB			0x27	/* R  , UART receive(big-end) buffer */
#define oUBRDIV			0x28	/* R/W, Baud rate divisor register */
/* Registers */
#define ULCON0			bUART(0, oULCON)
#define UCON0			bUART(0, oUCON)
#define UFCON0			bUART(0, oUFCON)
#define UMCON0			bUART(0, oUMCON)
#define UTRSTAT0		bUART(0, oUTRSTAT)
#define UERSTAT0		bUART(0, oUERSTAT)
#define UFSTAT0			bUART(0, oUFSTAT)
#define UMSTAT0			bUART(0, oUMSTAT)
#define UTXH0			bUART(0, oUTXHL)
#define URXH0			bUART(0, oURXHL)
#define UBRDIV0			bUART(0, oUBRDIV)
#define ULCON1			bUART(1, oULCON)
#define UCON1			bUART(1, oUCON)
#define UFCON1			bUART(1, oUFCON)
#define UMCON1			bUART(1, oUMCON)
#define UTRSTAT1		bUART(1, oUTRSTAT)
#define UERSTAT1		bUART(1, oUERSTAT)
#define UFSTAT1			bUART(1, oUFSTAT)
#define UMSTAT1			bUART(1, oUMSTAT)
#define UTXH1			bUART(1, oUTXHL)
#define URXH1			bUART(1, oURXHL)
#define UBRDIV1			bUART(1, oUBRDIV)
#define ULCON2			bUART(2, oULCON)
#define UCON2			bUART(2, oUCON)
#define UFCON2			bUART(2, oUFCON)
#define UMCON2			bUART(2, oUMCON)
#define UTRSTAT2		bUART(2, oUTRSTAT)
#define UERSTAT2		bUART(2, oUERSTAT)
#define UFSTAT2			bUART(2, oUFSTAT)
#define UMSTAT2			bUART(2, oUMSTAT)
#define UTXH2			bUART(2, oUTXHL)
#define URXH2			bUART(2, oURXHL)
#define UBRDIV2			bUART(2, oUBRDIV)
/* ... */
#define UTRSTAT_TX_EMPTY	(1 << 2)
#define UTRSTAT_RX_READY	(1 << 0)
#define UART_ERR_MASK		0xF 

#define ULCON_IR		(1 << 6)	/* use Infra-Red mode */

#define fULCON_PAR		Fld(3,3)	/* what parity mode? */
#define ULCON_PAR		FMsk(fULCON_PAR)
#define ULCON_PAR_NONE		FInsrt(0x0, fULCON_PAR) /* No Parity */
#define ULCON_PAR_ODD		FInsrt(0x4, fULCON_PAR) /* Odd Parity */
#define ULCON_PAR_EVEN		FInsrt(0x5, fULCON_PAR) /* Even Parity */
#define ULCON_PAR_1		FInsrt(0x6, fULCON_PAR) /* Parity force/checked as 1 */
#define ULCON_PAR_0		FInsrt(0x7, fULCON_PAR) /* Parity force/checked as 0 */

#define ULCON_STOP		(1 << 2)	/* The number of stop bits */
#define ULCON_ONE_STOP		(0 << 2)	/* 1 stop bit */
#define ULCON_TWO_STOP		(1 << 2)	/* 2 stop bit */

#define fULCON_WL		Fld(2, 0)	/* word length */
#define ULCON_WL		FMsk(fULCON_WL)
#define ULCON_WL5		FInsrt(0x0, fULCON_WL)	/* 5 bits */
#define ULCON_WL6		FInsrt(0x1, fULCON_WL)	/* 6 bits */
#define ULCON_WL7		FInsrt(0x2, fULCON_WL)	/* 7 bits */
#define ULCON_WL8		FInsrt(0x3, fULCON_WL)	/* 8 bits */

#define ULCON_CFGMASK		(ULCON_IR | ULCON_PAR | ULCON_WL)

#define UCON_CLK_SEL		(1 << 10)	/* select clock for UART */
#define UCON_CLK_PCLK		(0 << 10)	/* PCLK for UART baud rate */
#define UCON_CLK_UCLK		(1 << 10)	/* UCLK for UART baud rate */
#define UCON_TX_INT_TYPE	(1 << 9)	/* TX Interrupt request type */
#define UCON_TX_INT_PLS		(0 << 9)	/* Pulse */
#define UCON_TX_INT_LVL		(1 << 9)	/* Level */

#define UCON_RX_INT_TYPE	(1 << 8)	/* RX Interrupt request type */
#define UCON_RX_INT_PLS		(0 << 8)	/* Pulse */
#define UCON_RX_INT_LVL		(1 << 8)	/* Level */

#define UCON_RX_TIMEOUT		(1 << 7)	/* RX timeout enable */
#define UCON_RX_ERR_INT		(1 << 6)	/* RX error status interrupt enable */
#define UCON_LOOPBACK		(1 << 5)	/* to enter the loop-back mode */
#define UCON_BRK_SIG		(1 << 4)	/* to send a break during 1 frame time */

#define fUCON_TX	Fld(2,2)		/* function to write Tx data
						   to the UART Tx buffer */
#define UCON_TX		FMsk(fUCON_TX)
#define UCON_TX_DIS	FInsrt(0x0, fUCON_TX)	/* Disable */
#define UCON_TX_INT	FInsrt(0x1, fUCON_TX)	/* Interrupt or polling */
#define UCON_TX_DMA0	FInsrt(0x2, fUCON_TX)	/* DMA0 request */
#define UCON_TX_DMA1	FInsrt(0x3, fUCON_TX)	/* DMA1 request */

#define fUCON_RX	Fld(2,0)		/* function to read data
						   from UART Rx buffer */
#define UCON_RX		FMsk(fUCON_RX)
#define UCON_RX_DIS	FInsrt(0x0, fUCON_RX)	/* Disable */
#define UCON_RX_INT	FInsrt(0x1, fUCON_RX)	/* Interrupt or polling */
#define UCON_RX_DMA0	FInsrt(0x2, fUCON_RX)	/* DMA0 request */
#define UCON_RX_DMA1	FInsrt(0x3, fUCON_RX)	/* DMA1 request */

#define fUFCON_TX_TR	Fld(2,6)	/* trigger level of transmit FIFO */
#define UFCON_TX_TR	FMsk(fUFCON_TX_TR)
#define UFCON_TX_TR0	FInsrt(0x0, fUFCON_TX_TR)	/* Empty */
#define UFCON_TX_TR4	FInsrt(0x1, fUFCON_TX_TR)	/* 4-byte */
#define UFCON_TX_TR8	FInsrt(0x2, fUFCON_TX_TR)	/* 8-byte */
#define UFCON_TX_TR12	FInsrt(0x3, fUFCON_TX_TR)	/* 12-byte */

#define fUFCON_RX_TR	Fld(2,4)	/* trigger level of receive FIFO */
#define UFCON_RX_TR	FMsk(fUFCON_RX_TR)
#define UFCON_RX_TR0	FInsrt(0x0, fUFCON_RX_TR)	/* Empty */
#define UFCON_RX_TR4	FInsrt(0x1, fUFCON_RX_TR)	/* 4-byte */
#define UFCON_RX_TR8	FInsrt(0x2, fUFCON_RX_TR)	/* 8-byte */
#define UFCON_RX_TR12	FInsrt(0x3, fUFCON_RX_TR)	/* 12-byte */

#define UFCON_TX_REQ	(1 << 2)	/* auto-cleared after resetting FIFO */
#define UFCON_RX_REQ	(1 << 1)	/* auto-cleared after resetting FIFO */
#define UFCON_FIFO_EN	(1 << 0)	/* FIFO Enable */

#define UMCON_AFC	(1 << 4)	/* Enable Auto Flow Control */
#define UMCON_SEND	(1 << 0)	/* when not-AFC,
						set nRTS 1:'L' 0:'H' level */

#define UTRSTAT_TR_EMP	(1 << 2)	/* 1: Transmitter buffer &
						shifter register empty */
#define UTRSTAT_TX_EMP	(1 << 1)	/* Transmit buffer reg. is empty */
#define UTRSTAT_RX_RDY	(1 << 0)	/* Receive buffer reg. has data */

#define UERSTAT_BRK	(1 << 3)	/* Break receive */
#define UERSTAT_FRAME	(1 << 2)	/* Frame Error */
#define UERSTAT_PARITY	(1 << 1)	/* Parity Error */
#define UERSTAT_OVERRUN	(1 << 0)	/* Overrun Error */

#define UFSTAT_TX_FULL	(1 << 9)	/* Transmit FIFO is full */
#define UFSTAT_RX_FULL	(1 << 8)	/* Receive FIFO is full */

#define fUFSTAT_TX_CNT	Fld(4,4)	/* Number of data in Tx FIFO */
#define UFSTAT_TX_CNT	FMsk(fUFSTAT_TX_CNT)

#define fUFSTAT_RX_CNT	Fld(4,0)	/* Number of data in Rx FIFO */
#define UFSTAT_RX_CNT	FMsk(fUFSTAT_RX_CNT)

#define UMSTAT_dCTS	(1 << 3)	/* see Page 11-16 */
#define UMSTAT_CTS	(1 << 0)	/* CTS(Clear to Send) signal */

#define UTXH_DATA	0x000000FF	/* Transmit data for UARTn */
#define URXH_DATA	0x000000FF	/* Receive data for UARTn */
#define UBRDIVn		0x0000FFFF	/* Baud rate division value (> 0) */
/* UBRDIVn = (int)(PCLK/(bsp * 16)-1 or	UBRDIVn = (int)(UCLK/(bsp * 16)-1 */

/* Interrupts */
#define INT_CTL_BASE		0x4A000000
#define INTBASE			__REG(INT_CTL_BASE)
#define bINTCTL(Nb)		__REG(INT_CTL_BASE + (Nb))
/* Offset */
#define oSRCPND			0x00
#define oINTMOD			0x04
#define oINTMSK			0x08
#define oPRIORITY		0x0C
#define oINTPND			0x10
#define oINTOFFSET		0x14
#define oSUBSRCPND		0x18
#define oINTSUBMSK		0x1C
/* Registers */
#define SRCPND			bINTCTL(oSRCPND)
#define INTMOD			bINTCTL(oINTMOD)
#define INTMSK			bINTCTL(oINTMSK)
#define PRIORITY		bINTCTL(oPRIORITY)
#define INTPND			bINTCTL(oINTPND)
#define INTOFFSET		bINTCTL(oINTOFFSET)
#define SUBSRCPND		bINTCTL(oSUBSRCPND)
#define INTSUBMSK		bINTCTL(oINTSUBMSK)

#define INT_ADCTC		(1 << 31)	/* ADC EOC interrupt */
#define INT_RTC			(1 << 30)	/* RTC alarm interrupt */
#define INT_SPI1		(1 << 29)	/* UART1 transmit interrupt */
#define INT_UART0		(1 << 28)	/* UART0 transmit interrupt */
#define INT_IIC			(1 << 27)	/* IIC interrupt */
#define INT_USBH		(1 << 26)	/* USB host interrupt */
#define INT_USBD		(1 << 25)	/* USB device interrupt */
#define INT_RESERVED24		(1 << 24)
#define INT_UART1		(1 << 23)	/* UART1 receive interrupt */
#define INT_SPI0		(1 << 22)	/* SPI interrupt */
#define INT_MMC			(1 << 21)	/* MMC interrupt */
#define INT_DMA3		(1 << 20)	/* DMA channel 3 interrupt */
#define INT_DMA2		(1 << 19)	/* DMA channel 2 interrupt */
#define INT_DMA1		(1 << 18)	/* DMA channel 1 interrupt */
#define INT_DMA0		(1 << 17)	/* DMA channel 0 interrupt */
#define INT_LCD			(1 << 16)	/* reserved for future use */
#define INT_UART2		(1 << 15)	/* UART 2 interrupt  */
#define INT_TIMER4		(1 << 14)	/* Timer 4 interrupt */
#define INT_TIMER3		(1 << 13)	/* Timer 3 interrupt */
#define INT_TIMER2		(1 << 12)	/* Timer 2 interrupt */
#define INT_TIMER1		(1 << 11)	/* Timer 1 interrupt */
#define INT_TIMER0		(1 << 10)	/* Timer 0 interrupt */
#define INT_WDT			(1 << 9)	/* Watch-Dog timer interrupt */
#define INT_TICK		(1 << 8)	/* RTC time tick interrupt  */
#define INT_nBAT_FLT		(1 << 7)
#define INT_RESERVED6		(1 << 6)	/* Reserved for future use */
#define INT_EINT8_23		(1 << 5)	/* External interrupt 8 ~ 23 */
#define INT_EINT4_7		(1 << 4)	/* External interrupt 4 ~ 7 */
#define INT_EINT3		(1 << 3)	/* External interrupt 3 */
#define INT_EINT2		(1 << 2)	/* External interrupt 2 */
#define INT_EINT1		(1 << 1)	/* External interrupt 1 */
#define INT_EINT0		(1 << 0)	/* External interrupt 0 */

#define INT_ADC			(1 << 10)
#define INT_TC			(1 << 9)
#define INT_ERR2		(1 << 8)
#define INT_TXD2		(1 << 7)
#define INT_RXD2		(1 << 6)
#define INT_ERR1		(1 << 5)
#define INT_TXD1		(1 << 4)
#define INT_RXD1		(1 << 3)
#define INT_ERR0		(1 << 2)
#define INT_TXD0		(1 << 1)
#define INT_RXD0		(1 << 0)

/* Real Time Clock */
/* Registers */
#define bRTC(Nb)		__REG(0x57000000 + (Nb))
#define RTCCON			bRTC(0x40)
#define TICNT			bRTC(0x44)
#define RTCALM			bRTC(0x50)
#define ALMSEC			bRTC(0x54)
#define ALMMIN			bRTC(0x58)
#define ALMHOUR			bRTC(0x5c)
#define ALMDAY			bRTC(0x60)
#define ALMMON			bRTC(0x64)
#define ALMYEAR			bRTC(0x68)
#define RTCRST			bRTC(0x6c)
#define BCDSEC			bRTC(0x70)
#define BCDMIN			bRTC(0x74)
#define BCDHOUR			bRTC(0x78)
#define BCDDATE			bRTC(0x7c)
#define BCDDAY			bRTC(0x80)
#define BCDMON			bRTC(0x84)
#define BCDYEAR			bRTC(0x88)
/* Fields */
#define fRTC_SEC		Fld(7,0)
#define fRTC_MIN		Fld(7,0)
#define fRTC_HOUR		Fld(6,0)
#define fRTC_DAY		Fld(6,0)
#define fRTC_DATE		Fld(2,0)
#define fRTC_MON		Fld(5,0)
#define fRTC_YEAR		Fld(8,0)
/* Mask */
#define Msk_RTCSEC		FMsk(fRTC_SEC)
#define Msk_RTCMIN		FMsk(fRTC_MIN)
#define Msk_RTCHOUR		FMsk(fRTC_HOUR)
#define Msk_RTCDAY		FMsk(fRTC_DAY)
#define Msk_RTCDATE		FMsk(fRTC_DATE)
#define Msk_RTCMON		FMsk(fRTC_MON)
#define Msk_RTCYEAR		FMsk(fRTC_YEAR)
/* bits */
#define RTCCON_EN		(1 << 0) /* RTC Control Enable */
#define RTCCON_CLKSEL		(1 << 1) /* BCD clock as XTAL 1/2^25 clock */
#define RTCCON_CNTSEL		(1 << 2) /* 0: Merge BCD counters */
#define RTCCON_CLKRST		(1 << 3) /* RTC clock count reset */

/* RTC Alarm */
#define RTCALM_GLOBAL		(1 << 6) /* Global alarm enable */
#define RTCALM_YEAR		(1 << 5) /* Year alarm enable */
#define RTCALM_MON		(1 << 4) /* Month alarm enable */
#define RTCALM_DAY		(1 << 3) /* Day alarm enable */
#define RTCALM_HOUR		(1 << 2) /* Hour alarm enable */
#define RTCALM_MIN		(1 << 1) /* Minute alarm enable */
#define RTCALM_SEC		(1 << 0) /* Second alarm enable */
#define RTCALM_EN		(RTCALM_GLOBAL | RTCALM_YEAR | RTCALM_MON |\
				RTCALM_DAY | RTCALM_HOUR | RTCALM_MIN |\
				RTCALM_SEC)
#define RTCALM_DIS		(~RTCALM_EN)

/* PWM Timer */
#define bPWM_TIMER(Nb)		__REG(0x51000000 + (Nb))
#define bPWM_BUFn(Nb,x)		bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
/* Registers */
#define TCFG0			bPWM_TIMER(0x00)
#define TCFG1			bPWM_TIMER(0x04)
#define TCON			bPWM_TIMER(0x08)
#define TCNTB0			bPWM_BUFn(0,0x0)
#define TCMPB0			bPWM_BUFn(0,0x4)
#define TCNTO0			bPWM_BUFn(0,0x8)
#define TCNTB1			bPWM_BUFn(1,0x0)
#define TCMPB1			bPWM_BUFn(1,0x4)