s3c2410.h

武汉创维特公司的2410arm9开发办的can linux源代码

/*
 * linux/include/asm-arm/arch-s3c2410/S3C2410.h
 *
 * Definition of constants related to the S3C2410 microprocessor
 * This file is based on the S3C2410 User Manual 2002,01,23.
 *
 * Copyright (C) 2002 MIZI Research, Inc.
 *
 *  Author: Janghoon Lyu <[e-mail]>
 *  Date  : $Date: 2004/02/04 12:57:39 $
 *
 *  $Revision: 1.1.1.1 $
 *
   Tue May 14 2002 Janghoon Lyu <[e-mail]>
   - Initial code for VIVI
     
   Tue May 21 2002 Janghoon Lyu <[e-mail]>
   - add and modify for LINUX

   Wed Jul 24 2002 SeonKon Choi <[e-mail]>
   - add USB Device/Host
   - Errata (rev 0.1)

   Fri Aug 16 2002 Yong-iL Joh <[e-mail]>
   - add set_GPIO_mode(), GPCON(), GPDAT(x), GPUP()
   - add BWSCON_DW(x,y)
   - apply new irq scheme

   Fri Aug 16 2002 SeonKon Choi <[e-mail]>
   - add CLKCON bitfield

   Fri Aug 30 2002 Janghoon Lyu <[e-mail]>
   - add registers related to Power Management

   Mon Oct 14 2002 Janghoon Lyu <[e-mail]>
   - add the new gpio interface, and the remove old gpio interface


   Oct 27 '03 Kwanghyun La <[e-mail]> from laputa
   - add register & bit set macro for timer1 TCFG1

 *
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file COPYING in the main directory of this archive
 * for more details.
 */

#ifndef _S3C2410_H_
#define _S3C2410_H_

#include "hardware.h"
#include "bitfield.h"

/*
 * Memory Controller (Page 5-15)
 *
 * Register
   BWSCON	Bus Width & Wait Status Control	[word, R/W, 0x000000]
   BANKCON0	boot ROM Control		[word, R/W, 0x0700]
   BANKCON1	BANK1 Control			[word, R/W, 0x0700]
   BANKCON2	BANK2 Control			[word, R/W, 0x0700]
   BANKCON3	BANK3 Control			[word, R/W, 0x0700]
   BANKCON4	BANK4 Control			[word, R/W, 0x0700]
   BANKCON5	BANK5 Control			[word, R/W, 0x0700]
   BANKCON6	BANK6 Control			[word, R/W, 0x1808]
   BANKCON7	BANK7 Control			[word, R/W, 0x1808]
   REFRESH	DRAM/SDRAM Refresh Control	[word, R/W, 0xac0000]
   BANKSIZE	Flexible Bank Size		[word, R/W, 0x0]
   MRSRB6	Mode register set for SDRAM	[word, R/W]
   MRSRB7	Mode register set for SDRAM	[word, R/W]
 *
 */

#define bMEMCON(Nb)	__REG(0x48000000 + (Nb))
#define BWSCON		bMEMCON(0)
#define bBANKCON(Nb)	bMEMCON((Nb+1)*4)
#define BANKCON0	bBANKCON(0)
#define BANKCON1	bBANKCON(1)
#define BANKCON2	bBANKCON(2)
#define BANKCON3	bBANKCON(3)
#define BANKCON4	bBANKCON(4)
#define BANKCON5	bBANKCON(5)
#define BANKCON6	bBANKCON(6)
#define BANKCON7	bBANKCON(7)
#define REFRESH		bMEMCON(0x24)
#define BANKSIZE	bMEMCON(0x28)
#define MRSRB6		bMEMCON(0x2C)
#define MRSRB7		bMEMCON(0x30)

#define fBWSCON_ST(Nb)	Fld(1,((Nb)*4)+3)	/* Using UB/LB for Bank (Nb), init: 0 */
#define fBWSCON_WS(Nb)	Fld(1,((Nb)*4)+2)	/* WAIT enable for Bank (Nb), init: 0 */
#define fBWSCON_DW(Nb)	Fld(2,(Nb)*4)		/* data bus width for Bank (Nb), init: 0 */
#define fBWSCON_DW0	Fld(2,1)	/* initital state is undef */
#define BWSCON_ST7	FMsk(fBWSCON_ST(7))
#define BWSCON_WS7	FMsk(fBWSCON_WS(7))
#define BWSCON_DW7	FMsk(fBWSCON_DW(7))
#define BWSCON_ST6	FMsk(fBWSCON_ST(6))
#define BWSCON_WS6	FMsk(fBWSCON_WS(6))
#define BWSCON_DW6	FMsk(fBWSCON_DW(6))
#define BWSCON_ST5	FMsk(fBWSCON_ST(5))
#define BWSCON_WS5	FMsk(fBWSCON_WS(5))
#define BWSCON_DW5	FMsk(fBWSCON_DW(5))
#define BWSCON_ST4	FMsk(fBWSCON_ST(4))
#define BWSCON_WS4	FMsk(fBWSCON_WS(4))
#define BWSCON_DW4	FMsk(fBWSCON_DW(4))
#define BWSCON_ST3	FMsk(fBWSCON_ST(3))
#define BWSCON_WS3	FMsk(fBWSCON_WS(3))
#define BWSCON_DW3	FMsk(fBWSCON_DW(3))
#define BWSCON_ST2	FMsk(fBWSCON_ST(2))
#define BWSCON_WS2	FMsk(fBWSCON_WS(2))
#define BWSCON_DW2	FMsk(fBWSCON_DW(2))
#define BWSCON_ST1	FMsk(fBWSCON_ST(1))
#define BWSCON_WS1	FMsk(fBWSCON_WS(1))
#define BWSCON_DW1	FMsk(fBWSCON_DW(1))
#define BWSCON_DW0	FMsk(fBWSCON_DW0)
#define BWSCON_DW_8	0x0		/* set bus width to  8bit */
#define BWSCON_DW_16	0x1		/* set bus width to 16bit */
#define BWSCON_DW_32	0x2		/* set bus width to 32bit */
#define BWSCON_DW(x,y)	FInsrt((y), fBWSCON_DW(x))

#define	fBANKCON_Tacs	Fld(2,13)	/* Address set-up before nBCSn, init: 0 */
#define	BANKCON_Tacs	FMsk(fBANKCON_Tacs)
#define BANKCON_Tacs0	FInsrt(0x0, fBANKCON_Tacs)	/* 0 clock */
#define BANKCON_Tacs1	FInsrt(0x1, fBANKCON_Tacs)	/* 1 clock */
#define BANKCON_Tacs2	FInsrt(0x2, fBANKCON_Tacs)	/* 2 clock */
#define BANKCON_Tacs4	FInsrt(0x3, fBANKCON_Tacs)	/* 4 clock */

#define	fBANKCON_Tcos	Fld(2,11)	/* Chip selection set-up nOE, init: 0 */
#define	BANKCON_Tcos	FMsk(fBANKCON_Tcos)
#define BANKCON_Tcos0	FInsrt(0x0, fBANKCON_Tcos)	/* 0 clock */
#define BANKCON_Tcos1	FInsrt(0x1, fBANKCON_Tcos)	/* 1 clock */
#define BANKCON_Tcos2	FInsrt(0x2, fBANKCON_Tcos)	/* 2 clock */
#define BANKCON_Tcos4	FInsrt(0x3, fBANKCON_Tcos)	/* 4 clock */

#define	fBANKCON_Tacc	Fld(3,8)	/* Access cycle, init: 0x7 */
#define BANKCON_Tacc	FMsk(fBANKCON_Tacc)
#define BANKCON_Tacc1	FInsrt(0x0, fBANKCON_Tacc)	/* 1 clock */
#define BANKCON_Tacc2	FInsrt(0x1, fBANKCON_Tacc)	/* 2 clock */
#define BANKCON_Tacc3	FInsrt(0x2, fBANKCON_Tacc)	/* 3 clock */
#define BANKCON_Tacc4	FInsrt(0x3, fBANKCON_Tacc)	/* 4 clock */
#define BANKCON_Tacc6	FInsrt(0x4, fBANKCON_Tacc)	/* 6 clock */
#define BANKCON_Tacc8	FInsrt(0x5, fBANKCON_Tacc)	/* 8 clock */
#define BANKCON_Tacc10	FInsrt(0x6, fBANKCON_Tacc)	/* 10 clock */
#define BANKCON_Tacc14	FInsrt(0x7, fBANKCON_Tacc)	/* 14 clock */

#define	fBANKCON_Toch	Fld(2,6)	/* Chip selection hold on nOE, init: 0 */
#define	BANKCON_Toch	FMsk(fBANKCON_Toch)
#define BANKCON_Toch0	FInsrt(0x0, fBANKCON_Toch)	/* 0 clock */
#define BANKCON_Toch1	FInsrt(0x1, fBANKCON_Toch)	/* 1 clock */
#define BANKCON_Toch2	FInsrt(0x2, fBANKCON_Toch)	/* 2 clock */
#define BANKCON_Toch4	FInsrt(0x3, fBANKCON_Toch)	/* 4 clock */

#define	fBANKCON_Tcah	Fld(2,4)	/* Address holding time after nBCSn, init: 0 */
#define	BANKCON_Tcah	FMsk(fBANKCON_Tcah)
#define BANKCON_Tcah0	FInsrt(0x0, fBANKCON_Tcah)	/* 0 clock */
#define BANKCON_Tcah1	FInsrt(0x1, fBANKCON_Tcah)	/* 1 clock */
#define BANKCON_Tcah2	FInsrt(0x2, fBANKCON_Tcah)	/* 2 clock */
#define BANKCON_Tcah4	FInsrt(0x3, fBANKCON_Tcah)	/* 4 clock */

#define	fBANKCON_Tacp	Fld(2,2)	/* Page mode access cycle @ Page mode, init: 0 */
#define	BANKCON_Tacp	FMsk(fBANKCON_Tacp)
#define BANKCON_Tacp2	FInsrt(0x0, fBANKCON_Tacp)	/* 2 clock */
#define BANKCON_Tacp3	FInsrt(0x1, fBANKCON_Tacp)	/* 3 clock */
#define BANKCON_Tacp4	FInsrt(0x2, fBANKCON_Tacp)	/* 4 clock */
#define BANKCON_Tacp6	FInsrt(0x3, fBANKCON_Tacp)	/* 6 clock */

#define	fBANKCON_PMC	Fld(2,0)	/* Page mode configuration, init: 0 */
#define	BANKCON_PMC	FMsk(fBANKCON_PMC)
#define BANKCON_PMC1	FInsrt(0x0, fBANKCON_PMC)	/* normal (1 data) */
#define BANKCON_PMC4	FInsrt(0x1, fBANKCON_PMC)	/* 4 data */
#define BANKCON_PMC8	FInsrt(0x2, fBANKCON_PMC)	/* 8 data */
#define BANKCON_PMC16	FInsrt(0x3, fBANKCON_PMC)	/* 16 data */

#define fBANKCON_MT	Fld(2,15)	/* memory type for BANK6 and BANK7 */
#define BANKCON_MT	FMsk(fBANKCON_MT)
#define BANKCON_MT_ROM	FInsrt(0x0, fBANKCON_MT)	/* ROM or SRAM */
#define BANKCON_MT_EDO	FInsrt(0x2, fBANKCON_MT)	/* EDO DRAM */
#define BANKCON_MT_SDRM	FInsrt(0x3, fBANKCON_MT)	/* Sync. DRAM */

#define fBANKCON_Trcd	Fld(2,4)	/* RAS to CAS delay, init: 0 */
#define BANKCON_Trcd	FMsk(fBANKCON_Trcd)
#define BANKCON_Trcd1	FInsrt(0x0, fBANKCON_Trcd)	/* 1 clock */
#define BANKCON_Trcd2	FInsrt(0x1, fBANKCON_Trcd)	/* 2 clock */
#define BANKCON_Trcd3	FInsrt(0x2, fBANKCON_Trcd)	/* 3 clock */
#define BANKCON_Trcd4	FInsrt(0x3, fBANKCON_Trcd)	/* 4 clock */

#define fBANKCON_Tcas	Fld(1,3)	/* CAS pulse width, init: 0 */
#define BANKCON_Tcas	FMsk(fBANKCON_Tcas)
#define BANKCON_Tcas1	FInsrt(0x0, fBANKCON_Tcas)	/* 1 clock */
#define BANKCON_Tcas2	FInsrt(0x1, fBANKCON_Tcas)	/* 2 clock */

#define fBANKCON_Tcp	Fld(1,2)	/* CAS pre-charge, init: 0 */
#define BANKCON_Tcp	FMsk(fBANKCON_Tcp)
#define BANKCON_Tcp1	FInsrt(0x0, fBANKCON_Tcp)	/* 1 clock */
#define BANKCON_Tcp2	FInsrt(0x1, fBANKCON_Tcp)	/* 2 clock */

#define fBANKCON_CAN	Fld(2,0)	/* Column address number, init: 0 */
#define BANKCON_CAN	FMsk(fBANKCON_CAN)
#define BANKCON_CAN8	FInsrt(0x0, fBANKCON_CAN)	/* 8-bit */
#define BANKCON_CAN9	FInsrt(0x1, fBANKCON_CAN)	/* 9-bit */
#define BANKCON_CAN10	FInsrt(0x2, fBANKCON_CAN)	/* 10-bit */
#define BANKCON_CAN11	FInsrt(0x3, fBANKCON_CAN)	/* 11-bit */

#define fBANKCON_STrcd	Fld(2,2)	/* RAS to CAS delay, init: 0x2 */
#define BANKCON_STrcd	FMsk(fBANKCON_STrcd)
#define BANKCON_STrcd2	FInsrt(0x0, fBANKCON_STrcd)	/* 2 clock */
#define BANKCON_STrcd3	FInsrt(0x1, fBANKCON_STrcd)	/* 3 clock */
#define BANKCON_STrcd4	FInsrt(0x2, fBANKCON_STrcd)	/* 4 clock */

#define fBANKCON_SCAN	Fld(2,0)	/* Column address number, init: 0 */
#define BANKCON_SCAN	FMsk(fBANKCON_SCAN)
#define BANKCON_SCAN8	FInsrt(0x0, fBANKCON_SCAN)	/* 8-bit */
#define BANKCON_SCAN9	FInsrt(0x1, fBANKCON_SCAN)	/* 9-bit */
#define BANKCON_SCAN10	FInsrt(0x2, fBANKCON_SCAN)	/* 10-bit */

#define REFRESH_REFEN	(1 << 23)	/* DRAM/SDRAM Refresh Enable, init: 0x1 */

#define REFRESH_TREFMD	(1 << 22)	/* DRAM/SDRAM Refresh Mode, init: 0 */
#define REFRESH_TREFMD_Auto	(0 << 22)	/* CBR/Auto Refresh */
#define REFRESH_TREFMD_Self	(1 << 22)	/* Self Refresh */

#define fREFRESH_Trp	Fld(2,20)	/* DRAM/SDRAM RAS pre-charge, init: 0x2 */
#define REFRESH_Trp	FMsk(fREFRESH_Trp)
#define REFRESH_Trp15	FInsrt(0x0, fBANKCON_Trp)	/* DRAM : 1.5 clocks */
#define REFRESH_Trp25	FInsrt(0x1, fBANKCON_Trp)	/* DRAM : 2.5 clocks */
#define REFRESH_Trp35	FInsrt(0x2, fBANKCON_Trp)	/* DRAM : 3.5 clocks */
#define REFRESH_Trp45	FInsrt(0x3, fBANKCON_Trp)	/* DRAM : 4.5 clocks */
#define REFRESH_Trp2	FInsrt(0x0, fBANKCON_Trp)	/* SDRAM : 2 clocks */
#define REFRESH_Trp3	FInsrt(0x1, fBANKCON_Trp)	/* SDRAM : 3 clocks */
#define REFRESH_Trp4	FInsrt(0x2, fBANKCON_Trp)	/* SDRAM : 4 clocks */

#define fREFRESH_Trc	Fld(2,18)	/* SDRAM RC minimum time, init: 0x3 */
#define REFRESH_Trc	FMsk(fREFRESH_Trc)
#define REFRESH_Trc4	FInsrt(0x0, fBANKCON_Trc)	/* 4 clocks */
#define REFRESH_Trc5	FInsrt(0x1, fBANKCON_Trc)	/* 5 clocks */
#define REFRESH_Trc6	FInsrt(0x2, fBANKCON_Trc)	/* 6 clocks */
#define REFRESH_Trc7	FInsrt(0x3, fBANKCON_Trc)	/* 7 clocks */

#define fREFRESH_Tchr	Fld(2,18)	/* DRAM CAS hold time, init: 0 */
#define REFRESH_Tchr	FMsk(fREFRESH_Tchr)
#define REFRESH_Tchr1	FInsrt(0x0, fBANKCON_Tchr)	/* 1 clock */
#define REFRESH_Tchr2	FInsrt(0x1, fBANKCON_Tchr)	/* 2 clocks */
#define REFRESH_Tchr3	FInsrt(0x2, fBANKCON_Tchr)	/* 3 clocks */
#define REFRESH_Tchr4	FInsrt(0x3, fBANKCON_Tchr)	/* 4 clocks */

#define fREFRESH_RC	Fld(11,0)	/* DRAM/SDRAM Refresh Counter, init: 0 */
#define REFRESH_RC	FMsk(fREFRESH_RC)
#define REFRESH_RC_VALUE(refresh_period, HCLK) \
			(F1stBit(Fld(1,11)) + 1 - (HCLK)*(refresh_period))

#define fBANKSIZE_SCLK	Fld(1,4) /* SCLK is enable only during SDRAM access cycle
				    for reducing power cosumption.
				    When SDRAM isn't be accessed, SCLK is 'L' level.
				    0 = SCLK is always active
				    1 = SCLK is active only during the access
				    init: 0 */
#define BANKSIZE_SCLK	FMsk(fBANKSIZE_SCLK)

#define fBANKSIZE_MAP	Fld(2,0)	/* BANK6/7 memory map, init: 0 */
#define BANKSIZE_MAP	FMsk(fBANKSIZE_MAP)
#define BANKSIZE_MAP32	FInsrt(0x0, fBANKCON_MAP)	/* 32M/32M */
#define BANKSIZE_MAP2	FInsrt(0x4, fBANKCON_MAP)	/*  2M/ 2M */
#define BANKSIZE_MAP4	FInsrt(0x5, fBANKCON_MAP)	/*  4M/ 4M */
#define BANKSIZE_MAP8	FInsrt(0x6, fBANKCON_MAP)	/*  8M/ 8M */
#define BANKSIZE_MAP16	FInsrt(0x7, fBANKCON_MAP)	/* 16M/16M */

#define fMRSR_WBL	Fld(1,9)	/* Write burst length */
#define MRSR_WBL	FMsk(fMRSR_WBL)
#define	MRSR_WBL_Burst	FInsrt(0x0, fBANKCON_WBL)	/* Burst(Fixed) */

#define fMRSR_TM	Fld(2,7)	/* Test Mode */
#define MRSR_TM		FMsk(fMRSR_TM)
#define	MRSR_TM_Set	FInsrt(0x0, fBANKCON_TM)	/* Mode Register set(Fixed) */

#define fMRSR_CL	Fld(3,4)	/* CAS Latency */
#define MRSR_CL		FMsk(fMRSR_CL)
#define	MRSR_CL1	FInsrt(0x0, fBANKCON_CL)	/* 1 clock */
#define	MRSR_CL2	FInsrt(0x2, fBANKCON_CL)	/* 2 clocks */
#define	MRSR_CL3	FInsrt(0x3, fBANKCON_CL)	/* 3 clocks */

#define fMRSR_BT	Fld(1,3)	/* Burst Type */
#define MRSR_BT		FMsk(fMRSR_BT)
#define	MRSR_BT_Seq	FInsrt(0x0, fBANKCON_BT)	/* sequential(Fixed) */

#define fMRSR_BL	Fld(3,0)	/* Burst Length */
#define MRSR_BL		FMsk(fMRSR_BL)
#define	MRSR_BL1	FInsrt(0x0, fBANKCON_BL)	/* 1 (Fixed) */


/* Clock and Power Management */
#define CLK_CTL_BASE		0x4C000000
#define bCLKCTL(Nb)		__REG(CLK_CTL_BASE + (Nb))
/* Offset */
#define oLOCKTIME		0x00	/* R/W, PLL lock time count register */
#define oMPLLCON		0x04	/* R/W, MPLL configuration register */
#define oUPLLCON		0x08	/* R/W, UPLL configuration register */
#define oCLKCON			0x0C	/* R/W, Clock generator control reg. */
#define oCLKSLOW		0x10	/* R/W, Slow clock control register */
#define oCLKDIVN		0x14	/* R/W, Clock divider control */
/* Registers */
#define LOCKTIME		bCLKCTL(oLOCKTIME)
#define MPLLCON			bCLKCTL(oMPLLCON)
#define UPLLCON			bCLKCTL(oUPLLCON)
#define CLKCON			bCLKCTL(oCLKCON)
#define CLKSLOW			bCLKCTL(oCLKSLOW)
#define CLKDIVN			bCLKCTL(oCLKDIVN)

//laputa 030731 begine-->
//CLOCK SLOW CONTROL REGISTER ITEM 
//it's turn off the M/UPLL for power management 
#define UCLK_ON  (1<<7)    // 0:UCLK ON : ISERTED AUTOMATICALLY, 1: UCLK OFF
#define MPLL_OFF (1<<5)    // 0:PLL TURN ON 1:PLL IS TURN OFF
#define SLOW_BIT (1<<4)    // 0:FCLK=MPLL 1:SLOW MODE
//laputa append end <--

/* Fields */
#define fPLL_MDIV		Fld(8,12)
#define fPLL_PDIV		Fld(6,4)