signal_gen.mdl

matlab下

      Ports		      [1, 1]
      Position		      [510, 167, 570, 213]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Gain"
      SourceType	      "Gain AlteraBlockSet"
      vgain		      "127"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "0"
      pipeline		      "0"
      lpm		      off
      clken		      off
      MaskValue		      "1"
      gain		      "127"
    }
    Block {
      BlockType		      Reference
      Name		      "Increment\n"
      Ports		      [0, 1]
      Position		      [330, 318, 385, 362]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Increment\nDecrement"
      SourceType	      "IncDec AlteraBlockSet"
      BusType		      "Signed Integer"
      bwl		      "8"
      bwr		      "4"
      direction		      "Increment"
      cst_display	      "-127"
      cst		      "-127"
      clken		      off
      MaskValue		      "1"
      ntsamp		      "-1"
    }
    Block {
      BlockType		      Reference
      Name		      "Increment\nDecrement"
      Ports		      [0, 1]
      Position		      [170, 158, 225, 202]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Increment\nDecrement"
      SourceType	      "IncDec AlteraBlockSet"
      BusType		      "Unsigned Integer"
      bwl		      "8"
      bwr		      "4"
      direction		      "Increment"
      cst_display	      "0"
      cst		      "0"
      clken		      off
      MaskValue		      "1"
      ntsamp		      "-1"
    }
    Block {
      BlockType		      Reference
      Name		      "LUT"
      Ports		      [1, 1]
      Position		      [290, 158, 375, 202]
      ForegroundColor	      "blue"
      SourceBlock	      "gate_alteradspbuilder/LUT"
      SourceType	      "LUT  AlteraBlockSet"
      BusType		      "Unsigned Integer"
      bwl		      "8"
      bwr		      "0"
      bwaddr		      "8"
      MatlabArray	      "127*sin( [0:2*pi/(2^8):2*pi] )+128"
      LocPin		      "signal_genLUT"
      lpm		      on
      modulename	      "c:\\documents and settings\\oldslam\\桌面\\sign"
"al_gen\\DSPBuilder_signal_gen\\signal_genLUT.lut"
      pipeline		      off
      IslibDir		      "0"
      clken		      off
    }
    Block {
      BlockType		      Reference
      Name		      "Magnitude"
      Ports		      [1, 1]
      Position		      [625, 346, 670, 384]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Magnitude"
      SourceType	      "Magnitude Altera BlockSet"
    }
    Block {
      BlockType		      Reference
      Name		      "Parallel \nAdder Subtractor"
      Ports		      [2, 1]
      Position		      [555, 327, 590, 403]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Parallel \nAdder Subtra"
"ctor"
      SourceType	      "Sum AlteraBlockSet"
      Inputs		      "2"
      direction		      "++"
      pipeline		      on
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Product"
      Ports		      [2, 1]
      Position		      [445, 278, 510, 327]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product Altera BlockSet"
      pipeline		      "1"
      lpm		      on
      eab		      off
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Product1"
      Ports		      [2, 1]
      Position		      [430, 393, 495, 442]
      ForegroundColor	      "blue"
      SourceBlock	      "arithm_alteradspbuilder/Product"
      SourceType	      "Product Altera BlockSet"
      pipeline		      "1"
      lpm		      on
      eab		      off
      clken		      off
      MaskValue		      "1"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope"
      Ports		      [4]
      Position		      [705, 104, 795, 241]
      Location		      [5, 60, 1029, 741]
      Open		      on
      NumInputPorts	      "4"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
	axes4			"%<SignalLabel>"
      }
      List {
	ListType		SelectedSignals
	axes1			""
	axes2			""
	axes3			""
	axes4			""
      }
      YMin		      "-5~-5~-5~-5"
      YMax		      "5~5~5~5"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [174, 368, 243, 415]
      ForegroundColor	      "blue"
      SourceBlock	      "ALTELINK/AltLab/SignalCompiler"
      SourceType	      "SignalCompiler"
      family		      "Stratix"
      opt		      "Speed"
      synthtool		      "Others"
      vstim		      on
      SynthAct		      "None"
      workdir		      "c:\\documents and settings\\oldslam\\桌面\\sign"
"al_gen"
      Procetype		      "prod"
      UseReset		      on
      ResetPin		      "Active High"
      ClockPin		      "Output to Pin"
      ClockPeriod	      "20"
      UseSignalTap	      off
      CreatePtfFile	      off
      SignalTapDepth	      "128"
      VerilogSupport	      off
      UniqueVHDLHierarchyName off
      RegenerateIPFunctionalModel off
      RunUpdatedSimulation    off
    }
    Line {
      SrcBlock		      "Constant"
      SrcPort		      1
      Points		      [30, 0; 0, -40]
      DstBlock		      "Comparator"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Increment\nDecrement"
      SrcPort		      1
      Points		      [0, 0; 30, 0]
      Branch {
	DstBlock		"LUT"
	DstPort			1
      }
      Branch {
	Points			[0, 100; 50, 0]
	Branch {
	  DstBlock		  "Comparator1"
	  DstPort		  1
	}
	Branch {
	  Points		  [0, 115]
	  DstBlock		  "Comparator2"
	  DstPort		  1
	}
      }
      Branch {
	Points			[0, -60]
	DstBlock		"Scope"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "LUT"
      SrcPort		      1
      Points		      [30, 0]
      Branch {
	DstBlock		"Comparator"
	DstPort			1
      }
      Branch {
	Points			[0, -25]
	DstBlock		"Scope"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Constant1"
      SrcPort		      1
      Points		      [0, 0; 35, 0]
      Branch {
	DstBlock		"Comparator1"
	DstPort			2
      }
      Branch {
	Points			[0, 115]
	DstBlock		"Comparator2"
	DstPort			2
      }
    }
    Line {
      SrcBlock		      "Comparator1"
      SrcPort		      1
      DstBlock		      "Product"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Increment\n"
      SrcPort		      1
      Points		      [30, 0; 0, -25]
      DstBlock		      "Product"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Comparator2"
      SrcPort		      1
      DstBlock		      "Product1"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Decrement"
      SrcPort		      1
      Points		      [30, 0]
      DstBlock		      "Product1"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Product"
      SrcPort		      1
      Points		      [20, 0; 0, 40]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Product1"
      SrcPort		      1
      Points		      [35, 0; 0, -35]
      DstBlock		      "Parallel \nAdder Subtractor"
      DstPort		      2
    }
    Line {
      SrcBlock		      "Parallel \nAdder Subtractor"
      SrcPort		      1
      DstBlock		      "Magnitude"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Comparator"
      SrcPort		      1
      DstBlock		      "Gain"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Gain"
      SrcPort		      1
      DstBlock		      "Scope"
      DstPort		      3
    }
    Line {
      SrcBlock		      "Magnitude"
      SrcPort		      1
      Points		      [10, 0; 0, -140]
      DstBlock		      "Scope"
      DstPort		      4
    }
    Annotation {
      Position		      [564, 351]
    }
  }
}