top.edn

来自「Allegro原理图和PCB」· EDN 代码 · 共 1,844 行 · 第 1/5 页

EDN
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          (net (rename net_6 "net[6]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_6))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_6 "net_i[6]") (joined
           (portRef Y (instanceRef net_i_6))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_20 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(2:1)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_2 "net_i[2]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_1 "net[1]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_2 "net[2]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_2))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_2 "net_i[2]") (joined
           (portRef Y (instanceRef net_i_2))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_19 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(1:1)") 1) (direction OUTPUT))
           (port SW1_c (direction INPUT))
           (port CLK_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_1 "net_i[1]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_1 "net[1]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef A (instanceRef net_i_1))
           (portRef (member net 0))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net CLK_c (joined
           (portRef CLK_c)
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_1 "net_i[1]") (joined
           (portRef Y (instanceRef net_i_1))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_18 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(8:7)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_8 "net_i[8]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_7 "net[7]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_8 "net[8]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_8))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_8 "net_i[8]") (joined
           (portRef Y (instanceRef net_i_8))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_17 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(10:9)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_10 "net_i[10]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_9 "net[9]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_10 "net[10]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_10))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_10 "net_i[10]") (joined
           (portRef Y (instanceRef net_i_10))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_16 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(4:3)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_4 "net_i[4]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_3 "net[3]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_4 "net[4]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_4))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_4 "net_i[4]") (joined
           (portRef Y (instanceRef net_i_4))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_15 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(21:20)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_21 "net_i[21]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_20 "net[20]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_21 "net[21]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_21))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_21 "net_i[21]") (joined
           (portRef Y (instanceRef net_i_21))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_14 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename net "net(14:13)") 2) (direction INOUT))
           (port SW1_c (direction INPUT))
         )
         (contents
          (instance (rename net_i_14 "net_i[14]") (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net (rename net_13 "net[13]") (joined
           (portRef (member net 1))
           (portRef CLK (instanceRef Q_net))
          ))
          (net (rename net_14 "net[14]") (joined
           (portRef Q (instanceRef Q_net))
           (portRef (member net 0))
           (portRef A (instanceRef net_i_14))
          ))
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
          ))
          (net (rename net_iZ0Z_14 "net_i[14]") (joined
           (portRef Y (instanceRef net_i_14))
           (portRef D (instanceRef Q_net))
          ))
          (net VCC (joined
           (portRef Y (instanceRef VCC_i))
          ))
          (net GND (joined
           (portRef Y (instanceRef GND_i))
          ))
          (net (rename GNDZ0 "GND") (joined
           (portRef Y (instanceRef GND_i_0))
          ))
          (net (rename VCCZ0 "VCC") (joined
           (portRef Y (instanceRef VCC_i_0))
          ))
         )
       )
    )
    (cell clockdiv_13 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port SW1_c (direction INPUT))
           (port clk_internal1_0 (direction INPUT))
           (port clk_internal2 (direction OUTPUT))
         )
         (contents
          (instance clk_internal2_i (viewRef prim (cellRef INV (libraryRef PA3)))          )
          (instance Q_net (viewRef prim (cellRef DFN1C1 (libraryRef PA3)))
          )
          (instance VCC_i (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (instance VCC_i_0 (viewRef prim (cellRef VCC (libraryRef PA3)))          )
          (instance GND_i_0 (viewRef prim (cellRef GND (libraryRef PA3)))          )
          (net SW1_c (joined
           (portRef SW1_c)
           (portRef CLR (instanceRef Q_net))
12345

top.edn - 源码说明

本页面展示了「Allegro原理图和PCB」中的 top.edn 源码文件，采用 EDN 编程语言编写，共 1,844 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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