top.vhd

Allegro原理图和PCB

         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[9]_net_1\, CLK => net(8), CLR => SW1_c, 
        Q => net(9));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \net_i[9]\ : INV
      port map(A => net(9), Y => \net_i[9]_net_1\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_9 is

    port(net : 
        inout std_logic_vector(19 downto 18) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_9;

architecture DEF_ARCH of clockdiv_9 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \net_i[19]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \net_i[19]\ : INV
      port map(A => net(19), Y => \net_i[19]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[19]_net_1\, CLK => net(18), CLR => 
        SW1_c, Q => net(19));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_15 is

    port(net : 
        inout std_logic_vector(21 downto 20) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_15;

architecture DEF_ARCH of clockdiv_15 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[21]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[21]_net_1\, CLK => net(20), CLR => 
        SW1_c, Q => net(21));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \net_i[21]\ : INV
      port map(A => net(21), Y => \net_i[21]_net_1\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_18 is

    port(net : 
        inout std_logic_vector(8 downto 7) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_18;

architecture DEF_ARCH of clockdiv_18 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[8]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[8]_net_1\, CLK => net(7), CLR => SW1_c, 
        Q => net(8));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \net_i[8]\ : INV
      port map(A => net(8), Y => \net_i[8]_net_1\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_5 is

    port(net : 
        inout std_logic_vector(3 downto 2) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_5;

architecture DEF_ARCH of clockdiv_5 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \net_i[3]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \net_i[3]\ : INV
      port map(A => net(3), Y => \net_i[3]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[3]_net_1\, CLK => net(2), CLR => SW1_c, 
        Q => net(3));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_14 is

    port(net : 
        inout std_logic_vector(14 downto 13) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_14;

architecture DEF_ARCH of clockdiv_14 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \net_i[14]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \net_i[14]\ : INV
      port map(A => net(14), Y => \net_i[14]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[14]_net_1\, CLK => net(13), CLR => 
        SW1_c, Q => net(14));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_20 is

    port(net : 
        inout std_logic_vector(2 downto 1) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_20;

architecture DEF_ARCH of clockdiv_20 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \net_i[2]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \net_i[2]\ : INV
      port map(A => net(2), Y => \net_i[2]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[2]_net_1\, CLK => net(1), CLR => SW1_c, 
        Q => net(2));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_3 is

    port(net : 
        inout std_logic_vector(15 downto 14) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_3;

architecture DEF_ARCH of clockdiv_3 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[15]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[15]_net_1\, CLK => net(14), CLR => 
        SW1_c, Q => net(15));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \net_i[15]\ : INV
      port map(A => net(15), Y => \net_i[15]_net_1\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_2 is

    port(net : in std_logic_vector(21 to 21); SW1_c : in
         std_logic; clk_internal1, clk_internal1_0 : out
         std_logic);

end clockdiv_2;

architecture DEF_ARCH of clockdiv_2 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component BUFF
    port(A :