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Allegro原理图和PCB

        Q => \count[3]_net_1\);
    
    un1_count_3_I_18 : XOR2
      port map(A => \count[2]_net_1\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, Y => I_18);
    
    \state[1]\ : DFN1C1
      port map(D => \state_ns[7]\, CLK => lcd_en_0, CLR => SW1_c, 
        Q => \state[1]_net_1\);
    
    finished_1_sqmuxa_1_0_a5 : NOR3A
      port map(A => \lcd_data_12_sqmuxa_0_a3\, B => 
        \lcd_data_13_sqmuxa_0_a3\, C => \finished\, Y => 
        finished_1_sqmuxa_1);
    
    char_mode_process_display_char_14_m_1 : AO1
      port map(A => lcd_data_8_sqmuxa, B => lcd_data_14_sqmuxa, C
         => display_char_14, Y => display_char_14_m_1);
    
    \un1_display_char_14_2_iv[6]\ : OR3C
      port map(A => display_char_14_m_2, B => 
        \un1_display_char_14_2_iv_6[6]_net_1\, C => 
        \un1_display_char_14_2_iv_7[6]_net_1\, Y => 
        \un1_display_char_14_2_iv[6]_net_1\);
    
    \state_ns_a5[2]\ : AOI1B
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \state[5]_net_1\, Y => 
        state_1_sqmuxa_s5);
    
    \un1_display_char_14_2_iv_3[6]\ : NOR3B
      port map(A => \un1_display_char_13_m\, B => 
        \un1_char_mode_m[0]_net_1\, C => lcd_data_9_sqmuxa, Y => 
        \un1_display_char_14_2_iv_3[6]_net_1\);
    
    \un1_display_char_14_0_0[7]\ : NOR2B
      port map(A => lcd_data_14_sqmuxa, B => lcd_data_12_sqmuxa, 
        Y => \un1_display_char_14_0[7]\);
    
    \un1_char_mode_m[1]\ : OR2
      port map(A => lcd_data_4_sqmuxa, B => \char_mode[1]_net_1\, 
        Y => \un1_char_mode_m[1]_net_1\);
    
    \state_set_count_7[0]\ : NOR3C
      port map(A => N_131_i, B => \un1_state_4_i_i_0\, C => 
        \DWACT_ADD_CI_0_partial_sum[0]\, Y => \count_7[0]\);
    
    \state[8]\ : DFN1P1
      port map(D => \state_ns_i[0]_net_1\, CLK => lcd_en, PRE => 
        SW1_c, Q => \state[8]_net_1\);
    
    char_mode_process_display_char_14_m : AO1
      port map(A => N_160_1, B => 
        \un1_display_char_14_1[4]_net_1\, C => display_char_14, Y
         => display_char_14_m);
    
    un1_state_3_i : NOR3
      port map(A => N_159_1, B => \un1_state_3_i_0\, C => 
        \state_ns[7]\, Y => \un1_state_3_i\);
    
    \lcd_data[7]\ : DFN1E0
      port map(D => \un1_display_char_14_3_iv[7]_net_1\, CLK => 
        lcd_en_0, E => \un1_reset_1\, Q => LCD_net(7));
    
    \un1_display_char_14_3_iv_1[7]\ : NOR3A
      port map(A => \char_mode_m[0]_net_1\, B => \state_ns[4]\, C
         => finished_1_sqmuxa_1, Y => 
        \un1_display_char_14_3_iv_1[7]_net_1\);
    
    \un1_display_char_14_2_iv_7[6]\ : NOR3C
      port map(A => \un1_display_char_14_2_iv_3[6]_net_1\, B => 
        \un1_display_char_14_2_iv_2[6]_net_1\, C => 
        display_char_12_m, Y => 
        \un1_display_char_14_2_iv_7[6]_net_1\);
    
    \un1_char_mode_m[0]\ : OR3A
      port map(A => \lcd_data_12_sqmuxa_0_a3\, B => 
        \lcd_data_11_sqmuxa_0_o3\, C => \char_mode[0]_net_1\, Y
         => \un1_char_mode_m[0]_net_1\);
    
    lcd_data_12_sqmuxa_0_a3_0 : OR2A
      port map(A => \count[0]_net_1\, B => \count[2]_net_1\, Y
         => \lcd_data_12_sqmuxa_0_a3_0\);
    
    char_mode_process_display_char_14_m_0 : OR2
      port map(A => lcd_data_2_sqmuxa, B => display_char_14, Y
         => display_char_14_m_0);
    
    char_mode_process_display_char_14_m_2 : AO1
      port map(A => lcd_data_4_sqmuxa, B => 
        \un1_display_char_14_0[6]_net_1\, C => display_char_14, Y
         => display_char_14_m_2);
    
    \state_ns_a5[4]\ : NOR3C
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \state[5]_net_1\, Y => 
        \state_ns[4]\);
    
    char_mode_process_display_char_15_m : OR3C
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => display_char_15_m_0_0, Y
         => display_char_15_m);
    
    un1_state_7_0 : AO1C
      port map(A => \un1_state_7_0_a5_1\, B => \finished\, C => 
        \un1_state_7_0_a5_0\, Y => \un1_state_7_0\);
    
    state_set_char_mode_6_I_8 : XOR2
      port map(A => \char_mode[0]_net_1\, B => 
        finished_1_sqmuxa_1, Y => 
        \DWACT_ADD_CI_0_partial_sum_0[0]\);
    
    lcd_data_13_sqmuxa_0_a3 : OR2A
      port map(A => \count[2]_net_1\, B => \count[0]_net_1\, Y
         => \lcd_data_13_sqmuxa_0_a3\);
    
    char_mode_process_display_char_13_m_0_0 : OR2
      port map(A => \lcd_data_13_sqmuxa_0_a3\, B => 
        \lcd_data_6_sqmuxa_0_a3\, Y => display_char_13_m_0_0);
    
    un1_count_3_I_17 : XOR2
      port map(A => \count[3]_net_1\, B => I_21, Y => I_17);
    
    \un1_display_char_14_2_iv_7[4]\ : NOR2B
      port map(A => \un1_display_char_14_2_iv_4[4]_net_1\, B => 
        \un1_display_char_14_2_iv_5[4]_net_1\, Y => 
        \un1_display_char_14_2_iv_7[4]_net_1\);
    
    \lcd_rs\ : DFN1E0
      port map(D => lcd_rs_3, CLK => lcd_en, E => SW1_c, Q => 
        lcd_rs_net_1);
    
    un1_state_7_0_a5_1 : OR3
      port map(A => \state[1]_net_1\, B => \state[4]_net_1\, C
         => \state[7]_net_1\, Y => \un1_state_7_0_a5_1\);
    
    lcd_data_2_sqmuxa_0_a5 : OR2
      port map(A => \lcd_data_6_sqmuxa_0_a3\, B => 
        \lcd_data_12_sqmuxa_0_a3_0\, Y => lcd_data_2_sqmuxa);
    
    un1_count_3_I_19 : NOR2B
      port map(A => \DWACT_ADD_CI_0_TMP[0]\, B => 
        \count[1]_net_1\, Y => \DWACT_ADD_CI_0_g_array_1[0]\);
    
    \lcd_data[5]\ : DFN1E0
      port map(D => \un1_display_char_14_3_iv[5]_net_1\, CLK => 
        lcd_en_0, E => \un1_reset_1\, Q => LCD_net(5));
    
    lcd_data_14_sqmuxa_0_o3 : NOR2B
      port map(A => \count[2]_net_1\, B => \count[0]_net_1\, Y
         => \lcd_data_14_sqmuxa_0_o3\);
    
    \display_char_1_m[5]\ : AO1B
      port map(A => lcd_data_1_sqmuxa, B => lcd_data_6_sqmuxa, C
         => display_char_14, Y => \display_char_1_m[5]_net_1\);
    
    \char_mode[0]\ : DFN1C1
      port map(D => \DWACT_ADD_CI_0_partial_sum_0[0]\, CLK => 
        lcd_en_0, CLR => SW1_c, Q => \char_mode[0]_net_1\);
    
    un1_count_3_I_11 : XOR2
      port map(A => \count[0]_net_1\, B => \un1_state_3_i\, Y => 
        \DWACT_ADD_CI_0_partial_sum[0]\);
    
    state_set_lcd_rs_3_r : OA1A
      port map(A => \finished\, B => lcd_rs_net_1, C => 
        \state[2]_net_1\, Y => lcd_rs_3);
    
    lcd_data_0_sqmuxa_0_a5 : NOR2B
      port map(A => \state[2]_net_1\, B => \finished\, Y => 
        \state_ns[7]\);
    
    char_mode_process_display_char_15_m_0_0 : NOR3C
      port map(A => \char_mode[0]_net_1\, B => 
        \char_mode[1]_net_1\, C => \state[2]_net_1\, Y => 
        display_char_15_m_0_0);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \state_ns_a5_0[1]\ : OR3C
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \state[8]_net_1\, Y => 
        \state_ns_a5_0[1]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_6 is

    port(net : 
        inout std_logic_vector(7 downto 6) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_6;

architecture DEF_ARCH of clockdiv_6 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[7]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[7]_net_1\, CLK => net(6), CLR => SW1_c, 
        Q => net(7));
    
    \net_i[7]\ : INV
      port map(A => net(7), Y => \net_i[7]_net_1\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_23 is

    port(net : 
        inout std_logic_vector(5 downto 4) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_23;

architecture DEF_ARCH of clockdiv_23 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[5]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[5]_net_1\, CLK => net(4), CLR => SW1_c, 
        Q => net(5));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \net_i[5]\ : INV
      port map(A => net(5), Y => \net_i[5]_net_1\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_16 is

    port(net : 
        inout std_logic_vector(4 downto 3) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_16;

architecture DEF_ARCH of clockdiv_16 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \net_i[4]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \net_i[4]\ : INV
      port map(A => net(4), Y => \net_i[4]_net_1\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[4]_net_1\, CLK => net(3), CLR => SW1_c, 
        Q => net(4));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_17 is

    port(net : 
        inout std_logic_vector(10 downto 9) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_17;

architecture DEF_ARCH of clockdiv_17 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[10]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \net_i[10]_net_1\, CLK => net(9), CLR => 
        SW1_c, Q => net(10));
    
    \net_i[10]\ : INV
      port map(A => net(10), Y => \net_i[10]_net_1\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv_4 is

    port(net : 
        inout std_logic_vector(9 downto 8) := (others => 'Z'); 
        SW1_c : in std_logic);

end clockdiv_4;

architecture DEF_ARCH of clockdiv_4 is 

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \net_i[9]_net_1\, \VCC\, \GND\, GND_net_1, VCC_net_1