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Allegro原理图和PCB

    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component DFN1E0
    port(D, CLK, E : in std_logic := 'U'; Q : out std_logic);
  end component;

  component AOI1B
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OR2B
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component MX2C
    port(A, B, S : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component OA1B
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR2B
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR3A
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component DFN1P1
    port(D, CLK, PRE : in std_logic := 'U'; Q : out std_logic);
  end component;

  component AO1C
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal lcd_rs_net_1, \DWACT_ADD_CI_0_TMP[0]\, 
        \count[0]_net_1\, \un1_state_3_i\, I_17, \count[3]_net_1\, 
        I_21, \count_7[3]\, N_131_i, \un1_state_4_i_i_0\, 
        \state_ns[7]\, \state[2]_net_1\, \finished\, N_159_1, 
        \un1_state_3_i_0\, \DWACT_ADD_CI_0_g_array_1[0]\, 
        \count[2]_net_1\, \count[1]_net_1\, 
        \un1_display_char_14_0_1[7]_net_1\, lcd_data_4_sqmuxa, 
        lcd_data_6_sqmuxa, lcd_data_3_sqmuxa, 
        \un1_display_char_14_1[4]_net_1\, lcd_data_2_sqmuxa, 
        lcd_data_12_sqmuxa, \un1_display_char_14_2_iv[4]_net_1\, 
        \un1_display_char_14_2_iv_7[4]_net_1\, 
        \un1_display_char_14_2_iv_6[4]_net_1\, display_char_14_m, 
        \un1_display_char_14_3_iv[7]_net_1\, 
        \display_char_1_m_0[5]_net_1\, 
        \un1_display_char_14_3_iv_1[7]_net_1\, 
        display_char_15_m_0, lcd_data_8_sqmuxa, display_char_15, 
        N_160_1, display_char_14, \state_ns_o5[1]_net_1\, 
        \lcd_data_7_sqmuxa_0_o3\, \lcd_data_11_sqmuxa_0_o3\, 
        \char_mode_m[0]_net_1\, \state_ns[4]\, 
        finished_1_sqmuxa_1, 
        \un1_display_char_14_3_iv_4[5]_net_1\, 
        \un1_display_char_14_3_iv_2[5]_net_1\, 
        \display_char_1_m[5]_net_1\, N_156_1, 
        \un1_display_char_14_3_iv_0[5]_net_1\, 
        display_char_14_m_0, display_char_13_m, \state[0]_net_1\, 
        \state[3]_net_1\, \state[7]_net_1\, 
        \un1_display_char_14_2_iv_4[4]_net_1\, 
        \un1_display_char_14_2_iv_5[4]_net_1\, 
        \un1_display_char_14_2_iv_1[4]_net_1\, 
        \un1_display_char_14_2_iv_0[4]_net_1\, 
        \un1_char_mode_m[1]_net_1\, state_1_sqmuxa_s5, 
        lcd_data_7_sqmuxa, display_char_15_m, lcd_data_10_sqmuxa, 
        lcd_data_9_sqmuxa, \char_mode[1]_net_1\, 
        \un1_display_char_14_2_iv_7[6]_net_1\, 
        \un1_display_char_14_2_iv_3[6]_net_1\, 
        \un1_display_char_14_2_iv_2[6]_net_1\, display_char_12_m, 
        \un1_display_char_14_2_iv_6[6]_net_1\, 
        \un1_display_char_14_2_iv_4[6]_net_1\, 
        \char_mode[0]_net_1\, \un1_display_char_13_m\, 
        \un1_char_mode_m[0]_net_1\, \un1_display_char_14_0[7]\, 
        lcd_data_14_sqmuxa, \state[1]_net_1\, 
        \un1_display_char_14_0[6]_net_1\, 
        \lcd_data_13_sqmuxa_0_a3\, \lcd_data_14_sqmuxa_0_a3\, 
        lcd_data_1_sqmuxa, display_char_15_m_0_0, 
        \state[6]_net_1\, \state[4]_net_1\, display_char_13_m_0_0, 
        \lcd_data_6_sqmuxa_0_a3\, \un1_state_7_0_a5_1\, 
        \un1_display_char_14_3_iv[5]_net_1\, display_char_14_m_1, 
        \un1_display_char_14_2_iv[6]_net_1\, display_char_14_m_2, 
        display_char_13, \lcd_data_14_sqmuxa_0_o3\, 
        \lcd_data_12_sqmuxa_0_a3\, lcd_data_4_sqmuxa_1, 
        \lcd_data_12_sqmuxa_0_a3_0\, \un1_state_7_0_a5_0\, 
        \state_ns[6]_net_1\, \state[8]_net_1\, lcd_rs_3, 
        \un1_state_4_i_i_o5\, \state[5]_net_1\, \un1_state_7_0\, 
        \state_ns[2]_net_1\, \state_ns[1]_net_1\, 
        \state_ns_a5_0[1]_net_1\, \state_ns_i[0]_net_1\, 
        \count_7[2]\, I_18, \count_7[1]\, I_15, \count_7[0]\, 
        \DWACT_ADD_CI_0_partial_sum[0]\, \un1_reset_1\, 
        \DWACT_ADD_CI_0_partial_sum_0[0]\, \char_mode_6[1]\, 
        \DWACT_ADD_CI_0_TMP_0[0]\, \VCC\, \GND\, GND_net_1, 
        VCC_net_1 : std_logic;

begin 

    lcd_rs <= lcd_rs_net_1;

    \un1_display_char_14_2_1[5]\ : OR2
      port map(A => \state_ns[4]\, B => \state[8]_net_1\, Y => 
        N_156_1);
    
    state_set_char_mode_6_I_1 : AND2
      port map(A => \char_mode[0]_net_1\, B => 
        finished_1_sqmuxa_1, Y => \DWACT_ADD_CI_0_TMP_0[0]\);
    
    lcd_data_8_sqmuxa_0_a5 : OR3C
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \state[2]_net_1\, Y => 
        lcd_data_8_sqmuxa);
    
    \un1_display_char_14_2_iv_2[6]\ : NOR3
      port map(A => lcd_data_10_sqmuxa, B => N_159_1, C => 
        lcd_data_7_sqmuxa, Y => 
        \un1_display_char_14_2_iv_2[6]_net_1\);
    
    lcd_data_4_sqmuxa_0_a5_1 : NOR3B
      port map(A => \count[1]_net_1\, B => \state[2]_net_1\, C
         => \count[3]_net_1\, Y => lcd_data_4_sqmuxa_1);
    
    \count[1]\ : DFN1C1
      port map(D => \count_7[1]\, CLK => lcd_en_0, CLR => SW1_c, 
        Q => \count[1]_net_1\);
    
    char_mode_process_display_char_13 : OR2A
      port map(A => \char_mode[0]_net_1\, B => 
        \char_mode[1]_net_1\, Y => display_char_13);
    
    \un1_display_char_14_2_iv_0[4]\ : NOR2
      port map(A => \state[0]_net_1\, B => display_char_13_m, Y
         => \un1_display_char_14_2_iv_0[4]_net_1\);
    
    \state_set_count_7[1]\ : NOR3C
      port map(A => N_131_i, B => \un1_state_4_i_i_0\, C => I_15, 
        Y => \count_7[1]\);
    
    \char_mode_m[0]\ : OR3B
      port map(A => \lcd_data_12_sqmuxa_0_a3\, B => 
        \char_mode[0]_net_1\, C => \lcd_data_11_sqmuxa_0_o3\, Y
         => \char_mode_m[0]_net_1\);
    
    lcd_data_12_sqmuxa_0_a3 : NOR3C
      port map(A => \count[1]_net_1\, B => \count[3]_net_1\, C
         => \state[2]_net_1\, Y => \lcd_data_12_sqmuxa_0_a3\);
    
    \count[0]\ : DFN1C1
      port map(D => \count_7[0]\, CLK => lcd_en_0, CLR => SW1_c, 
        Q => \count[0]_net_1\);
    
    un1_display_char_13_m : OR3A
      port map(A => display_char_13, B => 
        \lcd_data_13_sqmuxa_0_a3\, C => \lcd_data_6_sqmuxa_0_a3\, 
        Y => \un1_display_char_13_m\);
    
    \state[7]\ : DFN1C1
      port map(D => \state_ns[1]_net_1\, CLK => lcd_en, CLR => 
        SW1_c, Q => \state[7]_net_1\);
    
    \state_ns[1]\ : AO1B
      port map(A => \state_ns_o5[1]_net_1\, B => \state[7]_net_1\, 
        C => \state_ns_a5_0[1]_net_1\, Y => \state_ns[1]_net_1\);
    
    state_set_char_mode_6_I_10 : XOR2
      port map(A => \char_mode[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP_0[0]\, Y => \char_mode_6[1]\);
    
    \state[5]\ : DFN1C1
      port map(D => \state[6]_net_1\, CLK => lcd_en, CLR => SW1_c, 
        Q => \state[5]_net_1\);
    
    \state[4]\ : DFN1C1
      port map(D => \state_ns[4]\, CLK => lcd_en, CLR => SW1_c, Q
         => \state[4]_net_1\);
    
    lcd_data_7_sqmuxa_0_a5 : NOR2A
      port map(A => lcd_data_4_sqmuxa_1, B => 
        \lcd_data_13_sqmuxa_0_a3\, Y => lcd_data_7_sqmuxa);
    
    \state[6]\ : DFN1C1
      port map(D => \state_ns[2]_net_1\, CLK => lcd_en, CLR => 
        SW1_c, Q => \state[6]_net_1\);
    
    \state[2]\ : DFN1C1
      port map(D => \state_ns[6]_net_1\, CLK => lcd_en, CLR => 
        SW1_c, Q => \state[2]_net_1\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    un1_state_4_i_i_0 : OA1C
      port map(A => \state[7]_net_1\, B => \state_ns_o5[1]_net_1\, 
        C => \state[1]_net_1\, Y => \un1_state_4_i_i_0\);
    
    un1_reset_1 : OR2
      port map(A => \state_ns[7]\, B => SW1_c, Y => \un1_reset_1\);
    
    \state_ns[2]\ : AO1A
      port map(A => \state_ns_o5[1]_net_1\, B => \state[7]_net_1\, 
        C => state_1_sqmuxa_s5, Y => \state_ns[2]_net_1\);
    
    lcd_data_4_sqmuxa_0_a5 : OR2A
      port map(A => lcd_data_4_sqmuxa_1, B => 
        \lcd_data_12_sqmuxa_0_a3_0\, Y => lcd_data_4_sqmuxa);
    
    \un1_display_char_14_3_iv_4[5]\ : NOR3B
      port map(A => \un1_display_char_14_3_iv_2[5]_net_1\, B => 
        \display_char_1_m[5]_net_1\, C => N_156_1, Y => 
        \un1_display_char_14_3_iv_4[5]_net_1\);
    
    char_mode_process_display_char_12_m : OR3
      port map(A => \char_mode[0]_net_1\, B => 
        \char_mode[1]_net_1\, C => lcd_data_8_sqmuxa, Y => 
        display_char_12_m);
    
    \state[3]\ : DFN1C1
      port map(D => \state[4]_net_1\, CLK => lcd_en, CLR => SW1_c, 
        Q => \state[3]_net_1\);
    
    lcd_data_14_sqmuxa_0_a3 : OR3B
      port map(A => \count[3]_net_1\, B => \state[2]_net_1\, C
         => \count[1]_net_1\, Y => \lcd_data_14_sqmuxa_0_a3\);
    
    lcd_data_6_sqmuxa_0_a5 : OR2A
      port map(A => \lcd_data_14_sqmuxa_0_o3\, B => 
        \lcd_data_6_sqmuxa_0_a3\, Y => lcd_data_6_sqmuxa);
    
    \state_ns[6]\ : AO1A
      port map(A => \finished\, B => \state[2]_net_1\, C => 
        N_159_1, Y => \state_ns[6]_net_1\);
    
    char_mode_process_display_char_15_m_0 : AO1
      port map(A => lcd_data_8_sqmuxa, B => 
        \un1_display_char_14_0_1[7]_net_1\, C => display_char_15, 
        Y => display_char_15_m_0);
    
    \un1_display_char_14_3_iv[7]\ : OR3C
      port map(A => \display_char_1_m_0[5]_net_1\, B => 
        \un1_display_char_14_3_iv_1[7]_net_1\, C => 
        display_char_15_m_0, Y => 
        \un1_display_char_14_3_iv[7]_net_1\);
    
    \state_ns_o5[1]\ : OR2A
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_11_sqmuxa_0_o3\, Y => \state_ns_o5[1]_net_1\);
    
    \un1_display_char_14_0_1[7]\ : NOR3C
      port map(A => lcd_data_4_sqmuxa, B => lcd_data_6_sqmuxa, C
         => lcd_data_3_sqmuxa, Y => 
        \un1_display_char_14_0_1[7]_net_1\);
    
    un1_count_3_I_1 : AND2
      port map(A => \count[0]_net_1\, B => \un1_state_3_i\, Y => 
        \DWACT_ADD_CI_0_TMP[0]\);
    
    lcd_data_11_sqmuxa_0_o3 : OR2
      port map(A => \count[2]_net_1\, B => \count[0]_net_1\, Y
         => \lcd_data_11_sqmuxa_0_o3\);
    
    un1_state_3_i_0 : OR2
      port map(A => \state[6]_net_1\, B => \state[4]_net_1\, Y
         => \un1_state_3_i_0\);
    
    \un1_display_char_14_1[7]\ : OA1
      port map(A => \lcd_data_13_sqmuxa_0_a3\, B => 
        \lcd_data_14_sqmuxa_0_a3\, C => lcd_data_1_sqmuxa, Y => 
        N_160_1);
    
    \state_set_count_7[2]\ : NOR3C
      port map(A => N_131_i, B => \un1_state_4_i_i_0\, C => I_18, 
        Y => \count_7[2]\);
    
    \un1_display_char_14_2_iv_6[6]\ : OA1A
      port map(A => display_char_15, B => lcd_data_3_sqmuxa, C
         => \un1_display_char_14_2_iv_4[6]_net_1\, Y => 
        \un1_display_char_14_2_iv_6[6]_net_1\);
    
    \lcd_data[6]\ : DFN1E0
      port map(D => \un1_display_char_14_2_iv[6]_net_1\, CLK => 
        lcd_en_0, E => \un1_reset_1\, Q => LCD_net(6));
    
    char_mode_process_display_char_13_m_0 : NOR2
      port map(A => display_char_13_m_0_0, B => display_char_13, 
        Y => display_char_13_m);
    
    \state_ns_i[0]\ : AOI1B
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \state[8]_net_1\, Y => 
        \state_ns_i[0]_net_1\);
    
    \lcd_data[4]\ : DFN1E0
      port map(D => \un1_display_char_14_2_iv[4]_net_1\, CLK => 
        lcd_en_0, E => \un1_reset_1\, Q => LCD_net(4));
    
    \display_char_1_m_0[5]\ : AO1B
      port map(A => N_160_1, B => \un1_display_char_14_0[7]\, C
         => display_char_14, Y => \display_char_1_m_0[5]_net_1\);
    
    lcd_data_7_sqmuxa_0_o3 : NOR2A
      port map(A => \count[1]_net_1\, B => \count[3]_net_1\, Y
         => \lcd_data_7_sqmuxa_0_o3\);
    
    \count[2]\ : DFN1C1
      port map(D => \count_7[2]\, CLK => lcd_en_0, CLR => SW1_c, 
        Q => \count[2]_net_1\);
    
    lcd_data_12_sqmuxa_0_a5 : OR2A
      port map(A => \lcd_data_12_sqmuxa_0_a3\, B => 
        \lcd_data_12_sqmuxa_0_a3_0\, Y => lcd_data_12_sqmuxa);
    
    \un1_display_char_14_2_iv[4]\ : OR3C
      port map(A => \un1_display_char_14_2_iv_7[4]_net_1\, B => 
        \un1_display_char_14_2_iv_6[4]_net_1\, C => 
        display_char_14_m, Y => 
        \un1_display_char_14_2_iv[4]_net_1\);
    
    un1_state_4_i_i_a5 : OR3C
      port map(A => \lcd_data_7_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_o3\, C => \un1_state_4_i_i_o5\, Y
         => N_131_i);
    
    \state[0]\ : DFN1C1
      port map(D => \state[1]_net_1\, CLK => lcd_en_0, CLR => 
        SW1_c, Q => \state[0]_net_1\);
    
    lcd_data_14_sqmuxa_0_a5 : OR2A
      port map(A => \lcd_data_14_sqmuxa_0_o3\, B => 
        \lcd_data_14_sqmuxa_0_a3\, Y => lcd_data_14_sqmuxa);
    
    \un1_display_char_14_3_iv[5]\ : OR2B
      port map(A => \un1_display_char_14_3_iv_4[5]_net_1\, B => 
        display_char_14_m_1, Y => 
        \un1_display_char_14_3_iv[5]_net_1\);
    
    \un1_display_char_14_0[6]\ : OA1
      port map(A => \lcd_data_13_sqmuxa_0_a3\, B => 
        \lcd_data_14_sqmuxa_0_a3\, C => lcd_data_1_sqmuxa, Y => 
        \un1_display_char_14_0[6]_net_1\);
    
    \un1_display_char_14_2_iv_1[4]\ : MX2C
      port map(A => lcd_data_10_sqmuxa, B => lcd_data_9_sqmuxa, S
         => \char_mode[1]_net_1\, Y => 
        \un1_display_char_14_2_iv_1[4]_net_1\);
    
    \un1_display_char_14_1[4]\ : NOR3C
      port map(A => lcd_data_2_sqmuxa, B => lcd_data_12_sqmuxa, C
         => lcd_data_3_sqmuxa, Y => 
        \un1_display_char_14_1[4]_net_1\);
    
    lcd_data_1_sqmuxa_0_a5 : OR2
      port map(A => \lcd_data_6_sqmuxa_0_a3\, B => 
        \lcd_data_11_sqmuxa_0_o3\, Y => lcd_data_1_sqmuxa);
    
    GND_i : GND
      port map(Y => \GND\);
    
    finished : DFN1E0
      port map(D => \un1_state_7_0\, CLK => lcd_en, E => SW1_c, Q
         => \finished\);
    
    \un1_display_char_14_1_1[6]\ : OR2
      port map(A => \state[3]_net_1\, B => \state[0]_net_1\, Y
         => N_159_1);
    
    lcd_data_9_sqmuxa_0_a5 : NOR2
      port map(A => \lcd_data_14_sqmuxa_0_a3\, B => 
        \lcd_data_11_sqmuxa_0_o3\, Y => lcd_data_9_sqmuxa);
    
    lcd_data_10_sqmuxa_0_a5 : NOR2
      port map(A => \lcd_data_14_sqmuxa_0_a3\, B => 
        \lcd_data_12_sqmuxa_0_a3_0\, Y => lcd_data_10_sqmuxa);
    
    \un1_display_char_14_2_iv_4[4]\ : AOI1B
      port map(A => display_char_15, B => lcd_data_7_sqmuxa, C
         => display_char_15_m, Y => 
        \un1_display_char_14_2_iv_4[4]_net_1\);
    
    lcd_data_6_sqmuxa_0_a3 : OR3A
      port map(A => \state[2]_net_1\, B => \count[1]_net_1\, C
         => \count[3]_net_1\, Y => \lcd_data_6_sqmuxa_0_a3\);
    
    \un1_display_char_14_2_iv_6[4]\ : NOR3B
      port map(A => \un1_display_char_14_2_iv_1[4]_net_1\, B => 
        \un1_display_char_14_2_iv_0[4]_net_1\, C => N_156_1, Y
         => \un1_display_char_14_2_iv_6[4]_net_1\);
    
    \un1_display_char_14_2_iv_4[6]\ : OA1B
      port map(A => \char_mode[0]_net_1\, B => lcd_data_12_sqmuxa, 
        C => \state_ns[4]\, Y => 
        \un1_display_char_14_2_iv_4[6]_net_1\);
    
    \un1_display_char_14_3_iv_2[5]\ : NOR3B
      port map(A => \un1_display_char_14_3_iv_0[5]_net_1\, B => 
        display_char_14_m_0, C => display_char_13_m, Y => 
        \un1_display_char_14_3_iv_2[5]_net_1\);
    
    un1_count_3_I_15 : XOR2
      port map(A => \count[1]_net_1\, B => 
        \DWACT_ADD_CI_0_TMP[0]\, Y => I_15);
    
    char_mode_process_display_char_15 : OR2B
      port map(A => \char_mode[1]_net_1\, B => 
        \char_mode[0]_net_1\, Y => display_char_15);
    
    un1_count_3_I_21 : NOR2B
      port map(A => \DWACT_ADD_CI_0_g_array_1[0]\, B => 
        \count[2]_net_1\, Y => I_21);
    
    un1_state_4_i_i_o5 : OR2
      port map(A => \state[8]_net_1\, B => \state[5]_net_1\, Y
         => \un1_state_4_i_i_o5\);
    
    \un1_display_char_14_2_iv_5[4]\ : NOR3B
      port map(A => lcd_data_6_sqmuxa, B => 
        \un1_char_mode_m[1]_net_1\, C => state_1_sqmuxa_s5, Y => 
        \un1_display_char_14_2_iv_5[4]_net_1\);
    
    \char_mode[1]\ : DFN1C1
      port map(D => \char_mode_6[1]\, CLK => lcd_en_0, CLR => 
        SW1_c, Q => \char_mode[1]_net_1\);
    
    \un1_display_char_14_3_iv_0[5]\ : NOR3
      port map(A => \state[0]_net_1\, B => \state[3]_net_1\, C
         => \state[7]_net_1\, Y => 
        \un1_display_char_14_3_iv_0[5]_net_1\);
    
    lcd_data_3_sqmuxa_0_a5 : OR2A
      port map(A => \state[2]_net_1\, B => \state_ns_o5[1]_net_1\, 
        Y => lcd_data_3_sqmuxa);
    
    char_mode_process_display_char_14 : OR2A
      port map(A => \char_mode[1]_net_1\, B => 
        \char_mode[0]_net_1\, Y => display_char_14);
    
    un1_state_7_0_a5_0 : OR3A
      port map(A => \lcd_data_12_sqmuxa_0_a3\, B => 
        \lcd_data_13_sqmuxa_0_a3\, C => \state[7]_net_1\, Y => 
        \un1_state_7_0_a5_0\);
    
    \state_set_count_7[3]\ : NOR3C
      port map(A => N_131_i, B => \un1_state_4_i_i_0\, C => I_17, 
        Y => \count_7[3]\);
    
    \count[3]\ : DFN1C1
      port map(D => \count_7[3]\, CLK => lcd_en_0, CLR => SW1_c,