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Allegro原理图和PCB

    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component XOR2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component AX1C
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \count_flashing[0]\, \count_flashing[1]\, 
        \count_flashing[2]\, \count_flashing_i[0]_net_1\, SUM2, 
        SUM1, \VCC\, \GND\, GND_net_1, VCC_net_1 : std_logic;

begin 

    count_flashing(2) <= \count_flashing[2]\;
    count_flashing(1) <= \count_flashing[1]\;
    count_flashing(0) <= \count_flashing[0]\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \Qaux[1]\ : DFN1C1
      port map(D => SUM1, CLK => clk_internal1, CLR => SW1_c, Q
         => \count_flashing[1]\);
    
    \Qaux[0]\ : DFN1C1
      port map(D => \count_flashing_i[0]_net_1\, CLK => 
        clk_internal1, CLR => SW1_c, Q => \count_flashing[0]\);
    
    \count_flashing_i[0]\ : INV
      port map(A => \count_flashing[0]\, Y => 
        \count_flashing_i[0]_net_1\);
    
    un3_qaux_1_SUM1 : XOR2
      port map(A => \count_flashing[1]\, B => \count_flashing[0]\, 
        Y => SUM1);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    \Qaux[2]\ : DFN1C1
      port map(D => SUM2, CLK => clk_internal1, CLR => SW1_c, Q
         => \count_flashing[2]\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    un3_qaux_1_SUM2 : AX1C
      port map(A => \count_flashing[0]\, B => \count_flashing[1]\, 
        C => \count_flashing[2]\, Y => SUM2);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity LED_Flashing is

    port(LED_Flashing_net : out std_logic_vector(7 downto 5); 
        clk_internal1, SW1_c : in std_logic; q7 : out std_logic);

        
end LED_Flashing;

architecture DEF_ARCH of LED_Flashing is 

  component VCC
    port(Y : out std_logic);
  end component;

  component OR3
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR3A
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component AXOI5
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component binary_counter
    port(count_flashing : out std_logic_vector(2 downto 0); SW1_c, 
        clk_internal1 : in std_logic := 'U');
  end component;

  component AXO2
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \count_flashing[0]\, \count_flashing[1]\, 
        \count_flashing[2]\, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

    for all : binary_counter
	Use entity work.binary_counter(DEF_ARCH);
begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    \q7\ : OR3
      port map(A => \count_flashing[0]\, B => \count_flashing[1]\, 
        C => \count_flashing[2]\, Y => q7);
    
    q11 : NOR3A
      port map(A => \count_flashing[2]\, B => \count_flashing[0]\, 
        C => \count_flashing[1]\, Y => LED_Flashing_net(7));
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    m2 : AXOI5
      port map(A => \count_flashing[0]\, B => \count_flashing[1]\, 
        C => \count_flashing[2]\, Y => LED_Flashing_net(6));
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    flashing_counter : binary_counter
      port map(count_flashing(2) => \count_flashing[2]\, 
        count_flashing(1) => \count_flashing[1]\, 
        count_flashing(0) => \count_flashing[0]\, SW1_c => SW1_c, 
        clk_internal1 => clk_internal1);
    
    m3 : AXO2
      port map(A => \count_flashing[0]\, B => \count_flashing[2]\, 
        C => \count_flashing[1]\, Y => LED_Flashing_net(5));
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity mux2 is

    port(count_net_0 : in std_logic_vector(7 downto 0); 
        LED_Flashing_net : in std_logic_vector(7 downto 5); 
        count_net : out std_logic_vector(7 downto 0); q7, 
        mux_select : in std_logic);

end mux2;

architecture DEF_ARCH of mux2 is 

  component MX2C
    port(A, B, S : in std_logic := 'U'; Y : out std_logic);
  end component;

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

    signal \VCC\, \GND\, GND_net_1, VCC_net_1 : std_logic;

begin 


    \Y[6]\ : MX2C
      port map(A => LED_Flashing_net(6), B => count_net_0(6), S
         => mux_select, Y => count_net(6));
    
    \Y[4]\ : MX2C
      port map(A => q7, B => count_net_0(4), S => mux_select, Y
         => count_net(4));
    
    \Y[1]\ : MX2C
      port map(A => LED_Flashing_net(6), B => count_net_0(1), S
         => mux_select, Y => count_net(1));
    
    \Y[7]\ : MX2C
      port map(A => LED_Flashing_net(7), B => count_net_0(7), S
         => mux_select, Y => count_net(7));
    
    \Y[5]\ : MX2C
      port map(A => LED_Flashing_net(5), B => count_net_0(5), S
         => mux_select, Y => count_net(5));
    
    \Y[3]\ : MX2C
      port map(A => q7, B => count_net_0(3), S => mux_select, Y
         => count_net(3));
    
    \Y[2]\ : MX2C
      port map(A => LED_Flashing_net(5), B => count_net_0(2), S
         => mux_select, Y => count_net(2));
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    \Y[0]\ : MX2C
      port map(A => LED_Flashing_net(7), B => count_net_0(0), S
         => mux_select, Y => count_net(0));
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity Data_Block is

    port(count_net_0 : out std_logic_vector(7 downto 0); HexB_c
         : in std_logic_vector(3 downto 0); HexA_c : 
        in std_logic_vector(3 downto 0); SW6_c, SW3_c_0, SW3_c, 
        clk_internal1_0, SW2_c, SW2_c_0, SW1_c, clk_internal1 : 
        in std_logic);

end Data_Block;

architecture DEF_ARCH of Data_Block is 

  component VCC
    port(Y : out std_logic);
  end component;

  component count8
    port(HexA_c : 
        in std_logic_vector(3 downto 0) := (others => 'U'); 
        HexB_c : 
        in std_logic_vector(3 downto 0) := (others => 'U'); 
        count_net : out std_logic_vector(7 downto 0); SW2_c_0, 
        SW2_c, clk_internal1_0, clk_internal1, SW3_c, SW1_c, 
        SW3_c_0 : in std_logic := 'U');
  end component;

  component clockdiv
    port(SW1_c, SW6_c : in std_logic := 'U'; mux_select : out
         std_logic);
  end component;

  component LED_Flashing
    port(LED_Flashing_net : out std_logic_vector(7 downto 5); 
        clk_internal1, SW1_c : in std_logic := 'U'; q7 : out
         std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component mux2
    port(count_net_0 : 
        in std_logic_vector(7 downto 0) := (others => 'U'); 
        LED_Flashing_net : 
        in std_logic_vector(7 downto 5) := (others => 'U'); 
        count_net : out std_logic_vector(7 downto 0); q7, 
        mux_select : in std_logic := 'U');
  end component;

    signal \LED_Flashing_net[5]\, \LED_Flashing_net[6]\, 
        \LED_Flashing_net[7]\, q7, \count_net[0]\, \count_net[1]\, 
        \count_net[2]\, \count_net[3]\, \count_net[4]\, 
        \count_net[5]\, \count_net[6]\, \count_net[7]\, 
        mux_select, \VCC\, \GND\, GND_net_1, VCC_net_1
         : std_logic;

    for all : count8
	Use entity work.count8(DEF_ARCH);
    for all : clockdiv
	Use entity work.clockdiv(DEF_ARCH);
    for all : LED_Flashing
	Use entity work.LED_Flashing(DEF_ARCH);
    for all : mux2
	Use entity work.mux2(DEF_ARCH);
begin 


    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    count8_intance : count8
      port map(HexA_c(3) => HexA_c(3), HexA_c(2) => HexA_c(2), 
        HexA_c(1) => HexA_c(1), HexA_c(0) => HexA_c(0), HexB_c(3)
         => HexB_c(3), HexB_c(2) => HexB_c(2), HexB_c(1) => 
        HexB_c(1), HexB_c(0) => HexB_c(0), count_net(7) => 
        \count_net[7]\, count_net(6) => \count_net[6]\, 
        count_net(5) => \count_net[5]\, count_net(4) => 
        \count_net[4]\, count_net(3) => \count_net[3]\, 
        count_net(2) => \count_net[2]\, count_net(1) => 
        \count_net[1]\, count_net(0) => \count_net[0]\, SW2_c_0
         => SW2_c_0, SW2_c => SW2_c, clk_internal1_0 => 
        clk_internal1_0, clk_internal1 => clk_internal1, SW3_c
         => SW3_c, SW1_c => SW1_c, SW3_c_0 => SW3_c_0);
    
    SW7_count : clockdiv
      port map(SW1_c => SW1_c, SW6_c => SW6_c, mux_select => 
        mux_select);
    
    LED_Flashing_instance : LED_Flashing
      port map(LED_Flashing_net(7) => \LED_Flashing_net[7]\, 
        LED_Flashing_net(6) => \LED_Flashing_net[6]\, 
        LED_Flashing_net(5) => \LED_Flashing_net[5]\, 
        clk_internal1 => clk_internal1, SW1_c => SW1_c, q7 => q7);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    
    DATA_MUX : mux2
      port map(count_net_0(7) => \count_net[7]\, count_net_0(6)
         => \count_net[6]\, count_net_0(5) => \count_net[5]\, 
        count_net_0(4) => \count_net[4]\, count_net_0(3) => 
        \count_net[3]\, count_net_0(2) => \count_net[2]\, 
        count_net_0(1) => \count_net[1]\, count_net_0(0) => 
        \count_net[0]\, LED_Flashing_net(7) => 
        \LED_Flashing_net[7]\, LED_Flashing_net(6) => 
        \LED_Flashing_net[6]\, LED_Flashing_net(5) => 
        \LED_Flashing_net[5]\, count_net(7) => count_net_0(7), 
        count_net(6) => count_net_0(6), count_net(5) => 
        count_net_0(5), count_net(4) => count_net_0(4), 
        count_net(3) => count_net_0(3), count_net(2) => 
        count_net_0(2), count_net(1) => count_net_0(1), 
        count_net(0) => count_net_0(0), q7 => q7, mux_select => 
        mux_select);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity lcd is

    port(LCD_net : out std_logic_vector(7 downto 4); lcd_en_0, 
        lcd_en, SW1_c : in std_logic; lcd_rs : out std_logic);

end lcd;

architecture DEF_ARCH of lcd is 

  component OR2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AND2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OR3C
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR3
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR3B
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component OR2A
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR3C
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OR3B
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OR3A
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AO1B
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component XOR2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR2A
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component VCC
    port(Y : out std_logic);
  end component;

  component OA1C
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AO1A
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OR3
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AO1
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OA1
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component OA1A