top.vhd

Allegro原理图和PCB

-- Version: 7.2 SPA 7.2.0.33

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity count8 is

    port(HexA_c : in std_logic_vector(3 downto 0); HexB_c : 
        in std_logic_vector(3 downto 0); count_net : 
        out std_logic_vector(7 downto 0); SW2_c_0, SW2_c, 
        clk_internal1_0, clk_internal1, SW3_c, SW1_c, SW3_c_0 : 
        in std_logic);

end count8;

architecture DEF_ARCH of count8 is 

  component XOR2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AO1A
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AND2
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component NOR2B
    port(A, B : in std_logic := 'U'; Y : out std_logic);
  end component;

  component AO1
    port(A, B, C : in std_logic := 'U'; Y : out std_logic);
  end component;

  component DFN1P1C1
    port(D, CLK, PRE, CLR : in std_logic := 'U'; Q : out
         std_logic);
  end component;

  component VCC
    port(Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

    signal \count_net[0]\, \count_net[1]\, \count_net[2]\, 
        \count_net[3]\, \count_net[4]\, \count_net[5]\, 
        \count_net[6]\, \count_net[7]\, \count_net_i[0]_net_1\, 
        un1_aclr_7_i, un1_aclr_6_i, un1_aclr_5_i, un1_aclr_4_i, 
        un1_aclr_3_i, un1_aclr_2_i, un1_aclr_1_i, un1_aclr_i, 
        \un1_sload_7\, \un1_sload_6\, \un1_sload_5\, 
        \un1_sload_4\, \un1_sload_3\, \un1_sload_2\, 
        \un1_sload_1\, \un1_sload\, \Qaux_5[1]\, \Qaux_5[2]\, 
        \Qaux_5[3]\, \Qaux_5[4]\, \Qaux_5[5]\, \Qaux_5[6]\, 
        \Qaux_5[7]\, \DWACT_ADD_CI_0_pog_array_1_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_0_3[0]\, 
        \DWACT_ADD_CI_0_pog_array_0_4[0]\, 
        \DWACT_ADD_CI_0_pog_array_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_0_1[0]\, 
        \DWACT_ADD_CI_0_pog_array_0_2[0]\, 
        \DWACT_ADD_CI_0_g_array_12_2[0]\, 
        \DWACT_ADD_CI_0_pog_array_0_5[0]\, 
        \DWACT_ADD_CI_0_g_array_11[0]\, 
        \DWACT_ADD_CI_0_g_array_0_6[0]\, 
        \DWACT_ADD_CI_0_g_array_12[0]\, 
        \DWACT_ADD_CI_0_g_array_1[0]\, 
        \DWACT_ADD_CI_0_g_array_0_2[0]\, 
        \DWACT_ADD_CI_0_g_array_12_1[0]\, 
        \DWACT_ADD_CI_0_g_array_2[0]\, 
        \DWACT_ADD_CI_0_g_array_0_4[0]\, 
        \DWACT_ADD_CI_0_g_array_1_2[0]\, 
        \DWACT_ADD_CI_0_g_array_0_5[0]\, 
        \DWACT_ADD_CI_0_g_array_1_1[0]\, 
        \DWACT_ADD_CI_0_g_array_0_3[0]\, 
        \DWACT_ADD_CI_0_pog_array_0[0]\, 
        \DWACT_ADD_CI_0_g_array_0_1[0]\, 
        \DWACT_ADD_CI_0_partial_sum[7]\, 
        \DWACT_ADD_CI_0_partial_sum[5]\, 
        \DWACT_ADD_CI_0_partial_sum[2]\, 
        \DWACT_ADD_CI_0_partial_sum[1]\, 
        \DWACT_ADD_CI_0_partial_sum[3]\, 
        \DWACT_ADD_CI_0_partial_sum[4]\, 
        \DWACT_ADD_CI_0_partial_sum[6]\, \VCC\, \GND\, GND_net_1, 
        VCC_net_1 : std_logic;

begin 

    count_net(7) <= \count_net[7]\;
    count_net(6) <= \count_net[6]\;
    count_net(5) <= \count_net[5]\;
    count_net(4) <= \count_net[4]\;
    count_net(3) <= \count_net[3]\;
    count_net(2) <= \count_net[2]\;
    count_net(1) <= \count_net[1]\;
    count_net(0) <= \count_net[0]\;

    Qaux_5_I_33 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[5]\, B => 
        \DWACT_ADD_CI_0_g_array_12_1[0]\, Y => \Qaux_5[5]\);
    
    un1_aclr : AO1A
      port map(A => HexA_c(3), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_i);
    
    Qaux_5_I_9 : AND2
      port map(A => \count_net[5]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_5[0]\);
    
    Qaux_5_I_20 : XOR2
      port map(A => \count_net[1]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[1]\);
    
    Qaux_5_I_16 : XOR2
      port map(A => \count_net[6]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_pog_array_0_5[0]\);
    
    Qaux_5_I_23 : XOR2
      port map(A => \count_net[3]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[3]\);
    
    Qaux_5_I_28 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[4]\, B => 
        \DWACT_ADD_CI_0_g_array_2[0]\, Y => \Qaux_5[4]\);
    
    un1_sload_1 : NOR2B
      port map(A => SW3_c, B => HexA_c(2), Y => \un1_sload_1\);
    
    Qaux_5_I_35 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0[0]\, B => 
        \count_net[0]\, C => \DWACT_ADD_CI_0_g_array_0_1[0]\, Y
         => \DWACT_ADD_CI_0_g_array_1[0]\);
    
    Qaux_5_I_37 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0_2[0]\, B => 
        \DWACT_ADD_CI_0_g_array_0_2[0]\, C => 
        \DWACT_ADD_CI_0_g_array_0_3[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_1_1[0]\);
    
    Qaux_5_I_11 : AND2
      port map(A => \count_net[3]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_3[0]\);
    
    Qaux_5_I_25 : XOR2
      port map(A => \count_net[5]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[5]\);
    
    Qaux_5_I_27 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[6]\, B => 
        \DWACT_ADD_CI_0_g_array_11[0]\, Y => \Qaux_5[6]\);
    
    \Qaux[5]\ : DFN1P1C1
      port map(D => \Qaux_5[5]\, CLK => clk_internal1_0, PRE => 
        \un1_sload_2\, CLR => un1_aclr_2_i, Q => \count_net[5]\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    Qaux_5_I_39 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_1_1[0]\, B => 
        \DWACT_ADD_CI_0_g_array_2[0]\, C => 
        \DWACT_ADD_CI_0_g_array_1_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_11[0]\);
    
    un1_aclr_6 : AO1A
      port map(A => HexB_c(1), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_6_i);
    
    \Qaux[6]\ : DFN1P1C1
      port map(D => \Qaux_5[6]\, CLK => clk_internal1_0, PRE => 
        \un1_sload_1\, CLR => un1_aclr_1_i, Q => \count_net[6]\);
    
    Qaux_5_I_34 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[7]\, B => 
        \DWACT_ADD_CI_0_g_array_12_2[0]\, Y => \Qaux_5[7]\);
    
    Qaux_5_I_40 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0_4[0]\, B => 
        \DWACT_ADD_CI_0_g_array_0_4[0]\, C => 
        \DWACT_ADD_CI_0_g_array_0_5[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_1_2[0]\);
    
    un1_sload_7 : NOR2B
      port map(A => SW3_c, B => HexB_c(0), Y => \un1_sload_7\);
    
    Qaux_5_I_6 : AND2
      port map(A => \count_net[2]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_2[0]\);
    
    un1_sload_4 : NOR2B
      port map(A => SW3_c, B => HexB_c(3), Y => \un1_sload_4\);
    
    Qaux_5_I_24 : XOR2
      port map(A => \count_net[4]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[4]\);
    
    un1_aclr_4 : AO1A
      port map(A => HexB_c(3), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_4_i);
    
    Qaux_5_I_10 : AND2
      port map(A => \count_net[6]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_6[0]\);
    
    Qaux_5_I_48 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_0_4[0]\, Y => 
        \DWACT_ADD_CI_0_pog_array_1_1[0]\);
    
    un1_aclr_1 : AO1A
      port map(A => HexA_c(2), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_1_i);
    
    un1_aclr_3 : AO1A
      port map(A => HexA_c(0), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_3_i);
    
    Qaux_5_I_18 : XOR2
      port map(A => \count_net[2]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_pog_array_0_1[0]\);
    
    un1_aclr_7 : AO1A
      port map(A => HexB_c(0), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_7_i);
    
    Qaux_5_I_32 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[2]\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, Y => \Qaux_5[2]\);
    
    un1_aclr_5 : AO1A
      port map(A => HexB_c(2), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_5_i);
    
    un1_aclr_2 : AO1A
      port map(A => HexA_c(1), B => SW3_c_0, C => SW1_c, Y => 
        un1_aclr_2_i);
    
    Qaux_5_I_45 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0_5[0]\, B => 
        \DWACT_ADD_CI_0_g_array_11[0]\, C => 
        \DWACT_ADD_CI_0_g_array_0_6[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_12_2[0]\);
    
    Qaux_5_I_47 : AND2
      port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => 
        \DWACT_ADD_CI_0_pog_array_0_2[0]\, Y => 
        \DWACT_ADD_CI_0_pog_array_1[0]\);
    
    Qaux_5_I_22 : XOR2
      port map(A => \count_net[7]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[7]\);
    
    \Qaux[4]\ : DFN1P1C1
      port map(D => \Qaux_5[4]\, CLK => clk_internal1_0, PRE => 
        \un1_sload_3\, CLR => un1_aclr_3_i, Q => \count_net[4]\);
    
    Qaux_5_I_15 : XOR2
      port map(A => \count_net[3]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_pog_array_0_2[0]\);
    
    Qaux_5_I_17 : XOR2
      port map(A => \count_net[4]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_pog_array_0_3[0]\);
    
    Qaux_5_I_5 : AND2
      port map(A => \count_net[1]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_1[0]\);
    
    GND_i : GND
      port map(Y => \GND\);
    
    \Qaux[0]\ : DFN1P1C1
      port map(D => \count_net_i[0]_net_1\, CLK => clk_internal1, 
        PRE => \un1_sload_7\, CLR => un1_aclr_7_i, Q => 
        \count_net[0]\);
    
    un1_sload : NOR2B
      port map(A => SW3_c, B => HexA_c(3), Y => \un1_sload\);
    
    Qaux_5_I_44 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0_1[0]\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, C => 
        \DWACT_ADD_CI_0_g_array_0_2[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_12[0]\);
    
    \Qaux[7]\ : DFN1P1C1
      port map(D => \Qaux_5[7]\, CLK => clk_internal1_0, PRE => 
        \un1_sload\, CLR => un1_aclr_i, Q => \count_net[7]\);
    
    \Qaux[2]\ : DFN1P1C1
      port map(D => \Qaux_5[2]\, CLK => clk_internal1_0, PRE => 
        \un1_sload_5\, CLR => un1_aclr_5_i, Q => \count_net[2]\);
    
    Qaux_5_I_14 : XOR2
      port map(A => \count_net[5]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_pog_array_0_4[0]\);
    
    Qaux_5_I_36 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_1[0]\, B => 
        \DWACT_ADD_CI_0_g_array_1[0]\, C => 
        \DWACT_ADD_CI_0_g_array_1_1[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_2[0]\);
    
    Qaux_5_I_7 : AND2
      port map(A => \count_net[4]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_g_array_0_4[0]\);
    
    Qaux_5_I_26 : XOR2
      port map(A => \count_net[6]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[6]\);
    
    Qaux_5_I_42 : AO1
      port map(A => \DWACT_ADD_CI_0_pog_array_0_3[0]\, B => 
        \DWACT_ADD_CI_0_g_array_2[0]\, C => 
        \DWACT_ADD_CI_0_g_array_0_4[0]\, Y => 
        \DWACT_ADD_CI_0_g_array_12_1[0]\);
    
    un1_sload_5 : NOR2B
      port map(A => SW3_c, B => HexB_c(2), Y => \un1_sload_5\);
    
    \Qaux[1]\ : DFN1P1C1
      port map(D => \Qaux_5[1]\, CLK => clk_internal1, PRE => 
        \un1_sload_6\, CLR => un1_aclr_6_i, Q => \count_net[1]\);
    
    Qaux_5_I_31 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[1]\, B => 
        \count_net[0]\, Y => \Qaux_5[1]\);
    
    Qaux_5_I_12 : XOR2
      port map(A => \count_net[1]\, B => SW2_c_0, Y => 
        \DWACT_ADD_CI_0_pog_array_0[0]\);
    
    un1_sload_6 : NOR2B
      port map(A => SW3_c, B => HexB_c(1), Y => \un1_sload_6\);
    
    Qaux_5_I_21 : XOR2
      port map(A => \count_net[2]\, B => SW2_c, Y => 
        \DWACT_ADD_CI_0_partial_sum[2]\);
    
    un1_sload_2 : NOR2B
      port map(A => SW3_c, B => HexA_c(1), Y => \un1_sload_2\);
    
    \Qaux[3]\ : DFN1P1C1
      port map(D => \Qaux_5[3]\, CLK => clk_internal1_0, PRE => 
        \un1_sload_4\, CLR => un1_aclr_4_i, Q => \count_net[3]\);
    
    un1_sload_3 : NOR2B
      port map(A => SW3_c, B => HexA_c(0), Y => \un1_sload_3\);
    
    \count_net_i[0]\ : INV
      port map(A => \count_net[0]\, Y => \count_net_i[0]_net_1\);
    
    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    Qaux_5_I_30 : XOR2
      port map(A => \DWACT_ADD_CI_0_partial_sum[3]\, B => 
        \DWACT_ADD_CI_0_g_array_12[0]\, Y => \Qaux_5[3]\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity clockdiv is

    port(SW1_c, SW6_c : in std_logic; mux_select : out std_logic);
        

end clockdiv;

architecture DEF_ARCH of clockdiv is 

  component VCC
    port(Y : out std_logic);
  end component;

  component INV
    port(A : in std_logic := 'U'; Y : out std_logic);
  end component;

  component GND
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

    signal \mux_select\, \mux_select_i\, \VCC\, \GND\, GND_net_1, 
        VCC_net_1 : std_logic;

begin 

    mux_select <= \mux_select\;

    VCC_i_0 : VCC
      port map(Y => VCC_net_1);
    
    mux_select_i : INV
      port map(A => \mux_select\, Y => \mux_select_i\);
    
    GND_i_0 : GND
      port map(Y => GND_net_1);
    
    Q_net : DFN1C1
      port map(D => \mux_select_i\, CLK => SW6_c, CLR => SW1_c, Q
         => \mux_select\);
    
    VCC_i : VCC
      port map(Y => \VCC\);
    
    GND_i : GND
      port map(Y => \GND\);
    

end DEF_ARCH; 

library ieee;
use ieee.std_logic_1164.all;
library proasic3;

entity binary_counter is

    port(count_flashing : out std_logic_vector(2 downto 0); SW1_c, 
        clk_internal1 : in std_logic);

end binary_counter;

architecture DEF_ARCH of binary_counter is 

  component VCC
    port(Y : out std_logic);
  end component;

  component DFN1C1
    port(D, CLK, CLR : in std_logic := 'U'; Q : out std_logic);
  end component;

  component INV