top.srr

Allegro原理图和PCB

@W:"c:\actelprj\pa3_demoboard_72\hdl\data_to_lcd.vhd":122:15:122:25|Net lcd_en_0 appears to be a clock source which was not identified. Assuming default frequency. 


##### START OF TIMING REPORT #####[
# Timing Report written on Mon Sep 18 16:29:52 2006
#


Top view:               TOP
Library name:           PA3
Operating conditions:   COMWC-2 ( T = 70.0, V = 1.40, P = 1.33, tree_type = balanced_tree )
Requested Frequency:    100.0 MHz
Wire load mode:         top
Wire load model:        PA3
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: -4.439

                   Requested     Estimated     Requested     Estimated                Clock        Clock              
Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group              
----------------------------------------------------------------------------------------------------------------------
TOP|CLK            100.0 MHz     444.7 MHz     10.000        2.249         7.751      inferred     Inferred_clkgroup_1
TOP|SW6            100.0 MHz     189.8 MHz     10.000        5.269         4.731      inferred     Inferred_clkgroup_2
System             100.0 MHz     69.3 MHz      10.000        14.439        -4.439     system       default_clkgroup   
======================================================================================================================





Clock Relationships
*******************

Clocks             |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
---------------------------------------------------------------------------------------------------------
Starting  Ending   |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
---------------------------------------------------------------------------------------------------------
TOP|CLK   TOP|CLK  |  10.000      7.751  |  No paths    -      |  No paths    -      |  No paths    -    
TOP|SW6   TOP|SW6  |  10.000      4.731  |  No paths    -      |  No paths    -      |  No paths    -    
=========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: TOP|CLK
====================================



Starting Points with Worst Slack
********************************

                                                  Starting                                    Arrival          
Instance                                          Reference     Type       Pin     Net        Time        Slack
                                                  Clock                                                        
---------------------------------------------------------------------------------------------------------------
CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net     TOP|CLK       DFN1C1     Q       net[1]     0.292       7.751
===============================================================================================================


Ending Points with Worst Slack
******************************

                                                  Starting                                      Required          
Instance                                          Reference     Type       Pin     Net          Time         Slack
                                                  Clock                                                           
------------------------------------------------------------------------------------------------------------------
CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net     TOP|CLK       DFN1C1     D       net_i[1]     9.590        7.751
==================================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.410
    = Required time:                         9.590

    - Propagation time:                      1.839
    = Slack (non-critical) :                 7.751

    Number of logic level(s):                1
    Starting point:                          CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net / Q
    Ending point:                            CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net / D
    The start point is clocked by            TOP|CLK [rising] on pin CLK
    The end   point is clocked by            TOP|CLK [rising] on pin CLK

Instance / Net                                                  Pin      Pin               Arrival     No. of    
Name                                                 Type       Name     Dir     Delay     Time        Fan Out(s)
-----------------------------------------------------------------------------------------------------------------
CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net        DFN1C1     Q        Out     0.292     0.292       -         
net[1]                                               Net        -        -       0.630     -           2(1)      
CLK_DIVIDER_intance.GEN_label.1.clk_div.net_i[1]     INV        A        In      -         0.922       -         
CLK_DIVIDER_intance.GEN_label.1.clk_div.net_i[1]     INV        Y        Out     0.287     1.209       -         
net_i[1]                                             Net        -        -       0.630     -           1         
CLK_DIVIDER_intance.GEN_label.1.clk_div.Q_net        DFN1C1     D        In      -         1.839       -         
=================================================================================================================
Total path delay (propagation time + setup) of 2.249 is 0.989(44.0%) logic and 1.260(56.0%) route.
Fanout format: logic fanout (physical fanout)




====================================
Detailed Report for Clock: TOP|SW6
====================================



Starting Points with Worst Slack
********************************

                                       Starting                                        Arrival          
Instance                               Reference     Type       Pin     Net            Time        Slack
                                       Clock                                                            
--------------------------------------------------------------------------------------------------------
Data_Block_intance.SW7_count.Q_net     TOP|SW6       DFN1C1     Q       mux_select     0.292       4.731
========================================================================================================


Ending Points with Worst Slack
******************************

                                       Starting                                          Required          
Instance                               Reference     Type       Pin     Net              Time         Slack
                                       Clock                                                               
-----------------------------------------------------------------------------------------------------------
Data_Block_intance.SW7_count.Q_net     TOP|SW6       DFN1C1     D       mux_select_i     9.590        4.731
===========================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        10.000
    - Setup time:                            0.410
    = Required time:                         9.590

    - Propagation time:                      4.859
    = Slack (non-critical) :                 4.731

    Number of logic level(s):                1
    Starting point:                          Data_Block_intance.SW7_count.Q_net / Q
    Ending point:                            Data_Block_intance.SW7_count.Q_net / D
    The start point is clocked by            TOP|SW6 [rising] on pin CLK