top.plg

来自「Allegro原理图和PCB」· PLG 代码 · 共 51 行

@P:  Worst Slack : -4.439
@P:  TOP|CLK - Estimated Frequency : 444.7 MHz
@P:  TOP|CLK - Requested Frequency : 100.0 MHz
@P:  TOP|CLK - Estimated Period : 2.249
@P:  TOP|CLK - Requested Period : 10.000
@P:  TOP|CLK - Slack : 7.751
@P:  TOP|SW6 - Estimated Frequency : 189.8 MHz
@P:  TOP|SW6 - Requested Frequency : 100.0 MHz
@P:  TOP|SW6 - Estimated Period : 5.269
@P:  TOP|SW6 - Requested Period : 10.000
@P:  TOP|SW6 - Slack : 4.731
@P:  System - Estimated Frequency : 69.3 MHz
@P:  System - Requested Frequency : 100.0 MHz
@P:  System - Estimated Period : 14.439
@P:  System - Requested Period : 10.000
@P:  System - Slack : -4.439
@P:  Total Area : 290.0
@P:  Total Area : 120.0
@P:  Total Area : 47.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 2.0
@P:  Total Area : 3.0
@P:  Total Area : 2.0
@P:  Total Area : 105.0
@P:  Total Area : 8.0
@P:  Total Area : 2.0
@P:  Total Area : 85.0
@P:  Total Area : 10.0
@P:  Total Area : 6.0
@P:  Total Area : 290.0
@P:  CPU Time : 0h:00m:01s