top_a3p250.stp

Allegro原理图和PCB

GOTO PRINT_PROGRAMMER_DONE;

PRINT_DIRECT_C_PROG:
PRINT "Programmer: DirectC";
GOTO PRINT_PROGRAMMER_DONE;

PRINT_ACTEL_JAM:
PRINT "Programmer: Actel JAM Player.";

PRINT_PROGRAMMER_DONE:
PRINT "=========================================";

ENDPROC;

PROCEDURE PROC_READ_IDCODE USES GV;
IRSCAN 8,$0F;
DRSCAN 32, $00000000,CAPTURE ID[];
EXPORT "IDCODE",ID[];
ENDPROC;

PROCEDURE DO_READ_IDCODE USES PROC_READ_IDCODE;
WAIT RESET, 5 CYCLES;
CALL PROC_READ_IDCODE;
EXIT 0;
ENDPROC;

PROCEDURE DO_QUERY_SECURITY USES DO_READ_SECURITY, DO_OUTPUT_SECURITY;
CALL DO_READ_SECURITY;
CALL DO_OUTPUT_SECURITY;
ENDPROC;
PROCEDURE POLL_PROGRAM USES GV;
' Check for program status
IRSTOP IDLE;
IRSCAN 8, $84;
IRSTOP IRPAUSE;

DRSTOP IDLE;
FOR i=0 TO 16380;
        WAIT 1 CYCLES;
        WAIT 100 USEC;
        'check for ROWBUSY and COLBUSY
        DRSCAN 5, #00000, COMPARE #00000,#01011, PASS;

    if PASS == 1 THEN i = 16380;
NEXT i;
DRSTOP DRPAUSE;
ENDPROC;
PROCEDURE POLL_ERASE USES GV;
  ' Check for erase status
  IRSTOP IDLE;
  IRSCAN 8, $84;
  IRSTOP IRPAUSE;

  DRSTOP IDLE;
  FOR i=0 TO 262140;
    WAIT 1 CYCLES;
    WAIT 1000 USEC;
    'check for ROWBUSY and COLBUSY
    DRSCAN 5, #00000, COMPARE #00000,#00011, PASS;

    if PASS == 1 THEN i = 262140;
  NEXT i;
  DRSTOP DRPAUSE;
ENDPROC;

PROCEDURE EXE_PROGRAM USES GV, DO_EXIT, POLL_PROGRAM;

    ' PROGRAM
    IRSTOP IDLE;
    IRSCAN 8, $83;
    IRSTOP IRPAUSE;
    WAIT 3 CYCLES;

    CALL POLL_PROGRAM;

    if PASS == 1 THEN GOTO Program_OK2;

    STATUS = 10;
    PRINT "Failed to program FPGA Array at row ", RowNumber, ".";
    CALL DO_EXIT;

    Program_OK2:

ENDPROC;

PROCEDURE EXE_VERIFY USES GV, DO_EXIT, POLL_PROGRAM;

    ' Verify0
    IRSCAN 8,$8D;
    DRSTOP IDLE;
    DRSCAN 2,VERIFY_EOL[];
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;
    WAIT 264 USEC;
    CALL POLL_PROGRAM;
    IRSCAN 8,$8D;
    DRSCAN 2, VERIFY_EOL[], COMPARE #00, #11, PASS ;  ' ISC_Verify_Result

    IF PASS THEN GOTO Verify_0_OK;

    STATUS =11;
    PRINT "Verify 0 failed"; 
    PRINT "Row Number : ", RowNumber;

    CALL DO_EXIT;

    Verify_0_OK:

    ' Verify1
    IRSCAN 8,$8E;
    DRSTOP IDLE;
    DRSCAN 2,VERIFY_EOL[];
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;
    WAIT 264 USEC;
    CALL POLL_PROGRAM;
    IRSCAN 8,$8E;
    DRSCAN 2, VERIFY_EOL[], COMPARE #00, #11, PASS ;  ' ISC_Verify_Result

    IF PASS THEN GOTO Verify_1_OK;

    STATUS =11;
    PRINT "Verify 1 failed"; 
    PRINT "Row Number : ", RowNumber;

    CALL DO_EXIT;

    Verify_1_OK:

ENDPROC;

PROCEDURE EXE_ERASE USES GV, DO_EXIT, PROC_PROGRAM_UROW, PROC_READ_UROW, BITSTREAM, POLL_ERASE;

IF !CombEraseSelect[14] THEN GOTO SkipRUrow;
    CALL PROC_READ_UROW;
    EXPORT "ACTEL_SLOG_UROW", UROW[];
SkipRUrow:

IRSCAN 8, $85;
DRSTOP IDLE;
DRSCAN 23, CombEraseSelect[];
DRSTOP DRPAUSE;

WAIT 3 CYCLES; 
CALL POLL_ERASE;

if PASS THEN GOTO EraseOK;
STATUS = 8;
PRINT "Failed Erase Operation";
CALL DO_EXIT;
EraseOK:

IF CombEraseSelect[14] THEN 
    CALL PROC_PROGRAM_UROW;

ENDPROC;

PROCEDURE DO_ERASE USES GV, EXE_ERASE;
PRINT "Erase ...";

CombEraseSelect[22..0] = $004000;

CombEraseSelect[0] = 1;

CALL EXE_ERASE;
ENDPROC;

PROCEDURE DO_ERASE_ARRAY USES GV, EXE_ERASE;
PRINT "Erase FPGA Array ...";

CombEraseSelect[22..0] = $004001;
CALL EXE_ERASE;

ENDPROC;

PROCEDURE DO_ERASE_ONLY USES GV, DO_ERASE;
IsEraseOnly = 1;
CALL DO_ERASE;
ENDPROC;

PROCEDURE DO_ERASE_ARRAY_ONLY USES GV, DO_ERASE_ARRAY;
IsEraseOnly = 1;
CALL DO_ERASE_ARRAY;
ENDPROC;

PROCEDURE DO_ERASE_ALL USES GV, EXE_ERASE;
IF 1 THEN PRINT "Erase FPGA Array, FlashROM and Security Settings ...";
IF !1 THEN PRINT "Erase FPGA Array and FlashROM ...";

CombEraseSelect[22..0] = #11111111100000000001111;
IsEraseOnly = 1;
CALL EXE_ERASE;

ENDPROC;

PROCEDURE DO_PROGRAM_RLOCK USES GV, POLL_PROGRAM, DO_EXIT;

    DataIndex = 0;
    IRSCAN 8,$89;

    DRSTOP IDLE;
    FOR SDNumber=1 TO 4;
        FOR i=1 TO 8;
            DRSCAN 26, rlock[DataIndex+25..DataIndex];
            WAIT 3 CYCLES;
            DataIndex = DataIndex + 26;
        NEXT i;
    NEXT SDNumber;

    DRSTOP DRPAUSE;

    IRSTOP IDLE;
    IRSCAN 8, $8C;
    IRSTOP IRPAUSE;
    WAIT 3 CYCLES;

    CALL POLL_PROGRAM;

    if PASS == 1 THEN GOTO Program_RLOCKOK;

    STATUS = 10;
    PRINT "Failed to program RLock.";
    CALL DO_EXIT;

    Program_RLOCKOK:

ENDPROC;

PROCEDURE DO_DEVICE_INFO USES GV, PROC_READ_UROW, PROC_DISPLAY_UROW, PROC_READ_FSN
;
    IRSCAN 8,$0E;
    DRSCAN 32, $00000000,CAPTURE Buff32[];

    EXPORT "SILSIG", Buff32[];
    CALL PROC_READ_UROW;
    CALL PROC_DISPLAY_UROW;
    CALL PROC_READ_FSN;
    EXPORT "FSN", Buff128[55..8];
    PRINT "=========================================";

ENDPROC;

PROCEDURE LOAD_ROW_DATA USES GV, BITSTREAM;
    ' Load one row of FPGA Array data.

    IRSCAN 8,$89;

    DRSTOP IDLE;
    FOR SDNumber=1 TO 4;
        FOR i=1 TO 8;
            DRSCAN 26, datastream[DataIndex+25..DataIndex];
            WAIT 3 CYCLES;
            DataIndex = DataIndex +26;
        NEXT i;
    NEXT SDNumber;
    DRSTOP DRPAUSE;

ENDPROC;

PROCEDURE DO_PROGRAM_SILSIG USES GV, DO_EXIT, DO_READ_SECURITY, POLL_PROGRAM;

    CALL DO_READ_SECURITY;

    SecReg[43..12] = SILSIG[31..0];

    SecReg[11] = ULOPT[1];
    SecReg[10] = ULOPT[0];
    SecReg[9] = ULUWE;
    SecReg[8] = ULARE;
    SecReg[7] = ULUPC;
    SecReg[6] = ULUFE;
    SecReg[5] = ULUFP;
    SecReg[4] = ULUFJ;
    SecReg[3] = ULFLR;
    SecReg[2] = ULULR;
    SecReg[1] = ULAWE;
    SecReg[0] = ULARD;

    IRSCAN 8, $A3;
    DRSTOP IDLE;
    DRSCAN 44, SecReg[];
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;

    CALL POLL_PROGRAM;

    if PASS == 1 THEN GOTO SilSigPrg_OK;

    STATUS = 14;
    PRINT "Failed to program Silicon Signature.";
    CALL DO_EXIT;

    SilSigPrg_OK:

ENDPROC;

PROCEDURE DO_VERIFY USES GV, BITSTREAM, EXE_VERIFY, LOAD_ROW_DATA;

'Reset Address
IRSCAN 8,$87;
DRSTOP IDLE;
DRSCAN 2, #10;
DRSTOP DRPAUSE;
WAIT 3 CYCLES;

PRINT "Verifying FPGA Array";
DataIndex=0;

FOR RowNumber=2300-1 TO 0 STEP -1;

    CALL LOAD_ROW_DATA;
    CALL EXE_VERIFY;

    ' Increment Address
    IRSCAN 8,$87;
    DRSTOP IDLE;
    DRSCAN 2, #11;
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;

    EXPORT "PERCENT_DONE", 100*(2300- RowNumber + 1)/2300;

NEXT RowNumber;

PRINT "    Verifying FPGA Array -- PASS";
ENDPROC;

PROCEDURE DO_VERIFY_BOL USES GV, DO_VERIFY;
VERIFY_EOL[0] = 0;
CALL DO_VERIFY;
ENDPROC;

PROCEDURE DO_VERIFY_EOL USES GV, DO_VERIFY;
VERIFY_EOL[0] = 1;
CALL DO_VERIFY;
ENDPROC;

PROCEDURE DO_PROGRAM USES GV, EXE_PROGRAM, LOAD_ROW_DATA;

'Reset Address
IRSCAN 8, $87;
DRSTOP IDLE;
DRSCAN 2, #10;
DRSTOP DRPAUSE;
WAIT 3 CYCLES;

PRINT "Programming FPGA Array";
DataIndex=0;
FOR RowNumber=2300-1 TO 0 STEP -1;

    CALL LOAD_ROW_DATA;
    CALL EXE_PROGRAM;

    ' Increment Address
    IRSCAN 8,$87;
    DRSTOP IDLE;
    DRSCAN 2, #11;
    DRSTOP DRPAUSE;
    WAIT 3 CYCLES;

    EXPORT "PERCENT_DONE", 100*(2300 - RowNumber + 1)/2300;

NEXT RowNumber;

ENDPROC;
CRC 3662;