led_flashing.vhd

Allegro原理图和PCB

-- LED_Flashind.vhd
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity LED_Flashing is
  port(Clock : in std_logic;
       Q : out std_logic_vector(7 downto 0);
       Aclr : in std_logic);
end LED_Flashing;

architecture behavioral of LED_Flashing is

  component binary_counter
    port(CLOCK : in std_logic; Q : out std_logic_vector(7 downto 0);
    ACLR : in std_logic);
  end component;

signal count_flashing :  std_logic_vector (2 downto 0);

begin

flashing_counter : binary_counter
      port map(CLOCK => Clock, Q =>  count_flashing, ACLR => ACLR);

  process (count_flashing)
  begin

    case count_flashing is
      when "000" => Q <= "00000000";
      when "001" => Q <= "00011000";
      when "010" => Q <= "00111100";
      when "011" => Q <= "01111110";
      when "100" => Q <= "11111111";
      when "101" => Q <= "01111110";
      when "110" => Q <= "00111100";
      when "111" => Q <= "00011000";
      when others => Q <= "00000000";
    end case;

  end process;



end behavioral;