dds-design.v

来自「FPGA_ASIC设计资料 代码集合」· Verilog 代码 · 共 45 行

/*******************************************************************
 *
 *    DESCRIPTION: DDS design BY PLD DEVICES.
 *
 *    AUTHOR: Sun Yu
 *
 *    HISTORY: 12/06/2002    
 *
 *******************************************************************/

 
module dds(sysclk, reset, freq_strobe, freq, select_out, signal_out);

// Program device signal and signal bus.
input			sysclk;			// system clock.               
input			reset;			// Global reset signal.
input			freq_strobe;	// Program device read strobe input.
input 	[31:0]	freq;			// define frequency using 32 bit.
output	[31:0]	select_out;
output 			signal_out;		// dds signal output.
//wire	[31:0]	phase;			// define phase accumulator using 32 bit.
reg 		[31:0]	phase;			// register variable.
//wire 	[31:0]	freq_out;
reg			[31:0]	freq_out;

always @ (posedge sysclk or posedge reset)
	begin
		if (reset)
			phase <= 32'h00000000;
		else
			phase <= phase + freq_out;
	end

always @ (posedge freq_strobe or posedge reset)
	begin
		if (reset)
			freq_out <= 32'h00000000;
		else
			freq_out <= freq;
	end

assign select_out = phase;
assign signal_out = phase[31:22] > 10'h1ff ? 1'b1 : 1'b0;

endmodule