📄 pcvt_ext.c

📁 freebsd v4.4内核源码
💻 C
📖 第 1 页 / 共 5 页
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		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, 0x83);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, 0x86);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, 0x9e);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, 0x89);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, 0x1c);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, 0x42);		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, 0x01);	/* 8 dot char clock */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */		outb(ATC_DATAW, 0x08);	/* Line graphics disable */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */		outb(ATC_DATAW, 0x00);		outb(TS_INDEX, TS_SYNCRESET);		outb(TS_DATA, 0x01);	/* synchronous reset */		outb(TS_INDEX, 0x83);		outb(TS_DATA, 0xa0);		outb(TS_INDEX, 0xa4);		outb(TS_DATA, 0x1c);		outb(TS_INDEX, 0xe0);		outb(TS_DATA, 0x00);		outb(TS_INDEX, 0xe4);		outb(TS_DATA, 0xfe);		outb(TS_INDEX, 0xf8);		outb(TS_DATA, 0x1b);		outb(TS_INDEX, 0xfd);		outb(TS_DATA, 0x33);		byte = inb(GN_MISCOUTR);		byte |= 0x0c;		outb(GN_MISCOUTW, byte);	/* Misc output register */		outb(TS_INDEX, TS_SYNCRESET);		outb(TS_DATA, 0x03);	/* clear synchronous reset */	}	else	/* switch 132 -> 80 */	{		if(!regsaved)			/* failsafe */		{			outb(TS_INDEX, TS_EXTCNTL);	/* disable extensions */			outb(TS_DATA, 0xae);			/* disable access to first 7 CRTC registers */			outb(addr_6845, CRTC_VSYNCE);			outb(addr_6845+1, byte);			vga_screen_on();			return(0);		}		sp = savearea.v7_1024i;		outb(addr_6845, 0x00);	/* Horizontal Total */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, *sp++);		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, *sp++);		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		/* ATC Mode control */		outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);		outb(ATC_DATAW, *sp++);		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		/* ATC Horizontal Pixel Panning */		outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);		outb(ATC_DATAW, *sp++);		outb(TS_INDEX, TS_SYNCRESET);		outb(TS_DATA, 0x01);	/* synchronous reset */		outb(TS_INDEX, 0x83);		outb(TS_DATA, *sp++);		outb(TS_INDEX, 0xa4);		outb(TS_DATA, *sp++);		outb(TS_INDEX, 0xe0);		outb(TS_DATA, *sp++);		outb(TS_INDEX, 0xe4);		outb(TS_DATA, *sp++);		outb(TS_INDEX, 0xf8);		outb(TS_DATA, *sp++);		outb(TS_INDEX, 0xfd);		outb(TS_DATA, *sp++);		outb(GN_MISCOUTW, *sp++);	/* Misc output register */		outb(TS_INDEX, TS_SYNCRESET);		outb(TS_DATA, 0x03);	/* clear synchronous reset */	}	outb(TS_INDEX, TS_EXTCNTL);	/* disable extensions */	outb(TS_DATA, 0xae);	/* disable access to first 7 CRTC registers */	outb(addr_6845, CRTC_VSYNCE);	outb(addr_6845+1, save__byte);	vga_screen_on();	return(1);}/*---------------------------------------------------------------------------* *	toggle 80/132 column operation for S3 86C928 based boards *---------------------------------------------------------------------------*/ints3_928_col(int cols){	u_char *sp;	u_char byte;	vga_screen_off();	outb(addr_6845, 0x38);	outb(addr_6845+1, 0x48);	/* unlock registers */	outb(addr_6845, 0x39);	outb(addr_6845+1, 0xa0);	/* unlock registers */	/* enable access to first 7 CRTC registers */	outb(addr_6845, CRTC_VSYNCE);	byte = inb(addr_6845+1);	outb(addr_6845, CRTC_VSYNCE);	outb(addr_6845+1, byte & 0x7f);	if(cols == SCR_COL132)		/* switch 80 -> 132 */	{		/* save state of board for 80 columns */		if(!regsaved)		{			regsaved = 1;			sp = savearea.s3_928;			outb(addr_6845, 0x00);	/* Horizontal Total */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x01);	/* Horizontal Display End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x02);	/* Horizontal Blank Start */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x03);	/* Horizontal Blank End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x04);	/* Horizontal Retrace Start */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x05);	/* Horizontal Retrace End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x13);	/* Row Offset Register */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x34);	/* Backward Compat 3 Reg */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x3b);	/* Data Xfer Exec Position */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x42);	/* (Clock) Mode Control */			*sp++ = inb(addr_6845+1);			outb(TS_INDEX, TS_MODE);/* Timing Sequencer */			*sp++ = inb(TS_DATA);			if(color)				inb(GN_INPSTAT1C);			else				inb(GN_INPSTAT1M);			/* ATC Mode control */			outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);			*sp++ = inb(ATC_DATAR);			if(color)				inb(GN_INPSTAT1C);			else				inb(GN_INPSTAT1M);			/* ATC Horizontal Pixel Panning */			outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);			*sp++ = inb(ATC_DATAR);			*sp++ = inb(GN_MISCOUTR);	/* Misc output register */		}		/* setup chipset for 132 column operation */		outb(addr_6845, 0x00);	/* Horizontal Total */		outb(addr_6845+1, 0x9a);		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, 0x83);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, 0x86);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, 0x9d);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, 0x87);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, 0x1b);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, 0x42);		outb(addr_6845, 0x34);		outb(addr_6845+1, 0x10);/* enable data xfer pos control */		outb(addr_6845, 0x3b);		outb(addr_6845+1, 0x90);/* set data xfer pos value */		outb(addr_6845, 0x42);	/* (Clock) Mode Control */		outb(addr_6845+1, 0x02);/* Select 40MHz Clock */		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, 0x01);	/* 8 dot char clock */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */		outb(ATC_DATAW, 0x08);	/* Line graphics disable */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */		outb(ATC_DATAW, 0x00);		/* Misc output register */		outb(GN_MISCOUTW, (inb(GN_MISCOUTR) | 0x0c));	}	else	/* switch 132 -> 80 */	{		if(!regsaved)			/* failsafe */		{			/* disable access to first 7 CRTC registers */			outb(addr_6845, CRTC_VSYNCE);			outb(addr_6845+1, byte);			outb(addr_6845, 0x38);			outb(addr_6845+1, 0x00);	/* lock registers */			outb(addr_6845, 0x39);			outb(addr_6845+1, 0x00);	/* lock registers */			vga_screen_on();			return(0);		}		sp = savearea.s3_928;		outb(addr_6845, 0x00);	/* Horizontal Total */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x34);		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x3b);		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x42);	/* Mode control */		outb(addr_6845+1, *sp++);		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, *sp++);		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		/* ATC Mode control */		outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);		outb(ATC_DATAW, *sp++);		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		/* ATC Horizontal Pixel Panning */		outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);		outb(ATC_DATAW, *sp++);		outb(GN_MISCOUTW, *sp++);	/* Misc output register */	}	/* disable access to first 7 CRTC registers */	outb(addr_6845, CRTC_VSYNCE);	outb(addr_6845+1, byte);	outb(addr_6845, 0x38);	outb(addr_6845+1, 0x00);	/* lock registers */	outb(addr_6845, 0x39);	outb(addr_6845+1, 0x00);	/* lock registers */	vga_screen_on();	return(1);}/*---------------------------------------------------------------------------* *	toggle 80/132 column operation for Cirrus Logic 542x based boards *---------------------------------------------------------------------------*/intcl_gd542x_col(int cols){	u_char *sp;	u_char byte;	vga_screen_off();	/* enable access to first 7 CRTC registers */	outb(addr_6845, CRTC_VSYNCE);	byte = inb(addr_6845+1);	outb(addr_6845, CRTC_VSYNCE);	outb(addr_6845+1, byte & 0x7f);	/* enable access to cirrus extension registers */	outb(TS_INDEX, 6);	outb(TS_DATA, 0x12);	if(cols == SCR_COL132)		/* switch 80 -> 132 */	{		/* save state of board for 80 columns */		if(!regsaved)		{			regsaved = 1;			sp = savearea.cirrus;			outb(addr_6845, 0x00);	/* Horizontal Total */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x01);	/* Horizontal Display End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x02);	/* Horizontal Blank Start */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x03);	/* Horizontal Blank End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x04);	/* Horizontal Retrace Start */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x05);	/* Horizontal Retrace End */			*sp++ = inb(addr_6845+1);			outb(addr_6845, 0x13);	/* Row Offset Register */			*sp++ = inb(addr_6845+1);			outb(TS_INDEX, TS_MODE);/* Timing Sequencer */			*sp++ = inb(TS_DATA);			if(color)				inb(GN_INPSTAT1C);			else				inb(GN_INPSTAT1M);			/* ATC Mode control */			outb(ATC_INDEX, ATC_MODE | ATC_ACCESS);			*sp++ = inb(ATC_DATAR);			if(color)				inb(GN_INPSTAT1C);			else				inb(GN_INPSTAT1M);			/* ATC Horizontal Pixel Panning */			outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS);			*sp++ = inb(ATC_DATAR);			/* VCLK2 Numerator Register */			outb(TS_INDEX, 0xd);			*sp++ = inb(TS_DATA);			/* VCLK2 Denominator and Post-Scalar Value Register */			outb(TS_INDEX, 0x1d);			*sp++ = inb(TS_DATA);			/* Misc output register */			*sp++ = inb(GN_MISCOUTR);		}		/* setup chipset for 132 column operation */		outb(addr_6845, 0x00);	/* Horizontal Total */		outb(addr_6845+1, 0x9f);		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, 0x83);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, 0x84);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, 0x82);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, 0x8a);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, 0x9e);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, 0x42);		/* set VCLK2 to 41.164 MHz ..... */		outb(TS_INDEX, 0xd);	/* VCLK2 Numerator Register */		outb(TS_DATA, 0x45);		outb(TS_INDEX, 0x1d);	/* VCLK2 Denominator and */		outb(TS_DATA, 0x30);   /* Post-Scalar Value Register */		/* and use it. */		outb(GN_MISCOUTW, (inb(GN_MISCOUTR) & ~0x0c) | (2 << 2));		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, 0x01);	/* 8 dot char clock */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_MODE | ATC_ACCESS); /* ATC Mode control */		outb(ATC_DATAW, 0x08);	/* Line graphics disable */		if(color)			inb(GN_INPSTAT1C);		else			inb(GN_INPSTAT1M);		outb(ATC_INDEX, ATC_HORPIXPAN | ATC_ACCESS); /* ATC Horizontal Pixel Panning */		outb(ATC_DATAW, 0x00);	}	else	/* switch 132 -> 80 */	{		if(!regsaved)			/* failsafe */		{			/* disable access to first 7 CRTC registers */			outb(addr_6845, CRTC_VSYNCE);			outb(addr_6845+1, byte);			/* disable access to cirrus extension registers */			outb(TS_INDEX, 6);			outb(TS_DATA, 0);			vga_screen_on();			return(0);		}		sp = savearea.cirrus;		outb(addr_6845, 0x00);	/* Horizontal Total */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x01);	/* Horizontal Display End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x02);	/* Horizontal Blank Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x03);	/* Horizontal Blank End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x04);	/* Horizontal Retrace Start */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x05);	/* Horizontal Retrace End */		outb(addr_6845+1, *sp++);		outb(addr_6845, 0x13);	/* Row Offset Register */		outb(addr_6845+1, *sp++);		outb(TS_INDEX, TS_MODE);/* Timing Sequencer */		outb(TS_DATA, *sp++);
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