pcvt_hdr.h

freebsd v4.4内核源码

#define VT_INVERSE	0x08		/* inverse attribute */

/*---------------------------------------------------------------------------*
 *	VGA GENERAL/EXTERNAL Registers          (3BA or 3DA and 3CA, 3C2, 3CC)
 *---------------------------------------------------------------------------*/

#define GN_MISCOUTR	0x3CC		/* misc output register read */
#define GN_MISCOUTW	0x3C2		/* misc output register write */
#define GN_INPSTAT0	0x3C2		/* input status 0, r/o */
#define GN_INPSTAT1M	0x3BA		/* input status 1, r/o, mono */
#define GN_INPSTAT1C	0x3DA		/* input status 1, r/o, color */
#define GN_FEATR	0x3CA		/* feature control, read */
#define GN_FEATWM	0x3BA		/* feature control, write, mono */
#define GN_FEATWC	0x3DA		/* feature control, write, color */
#define GN_VSUBSYS	0x3C3		/* video subsystem register r/w */
#define GN_DMCNTLM	0x3B8		/* display mode control, r/w, mono */
#define GN_DMCNTLC	0x3D8		/* display mode control, r/w, color */
#define GN_COLORSEL	0x3D9		/* color select register, w/o */
#define GN_HERCOMPAT	0x3BF		/* Hercules compatibility reg, w/o */

/*---------------------------------------------------------------------------*
 *	VGA CRTC Registers			  (3B4 and 3B5 or 3D4 and 3D5)
 *---------------------------------------------------------------------------*/

#define MONO_BASE	0x3B4		/* crtc index register address mono */
#define CGA_BASE	0x3D4		/* crtc index register address color */

#define	CRTC_ADDR	0x00		/* index register */

#define CRTC_HTOTAL	0x00		/* horizontal total */
#define CRTC_HDISPLE	0x01		/* horizontal display end */
#define CRTC_HBLANKS	0x02		/* horizontal blank start */
#define CRTC_HBLANKE	0x03		/* horizontal blank end */
#define CRTC_HSYNCS	0x04		/* horizontal sync start */
#define CRTC_HSYNCE	0x05		/* horizontal sync end */
#define CRTC_VTOTAL	0x06		/* vertical total */
#define CRTC_OVERFLL	0x07		/* overflow low */
#define CRTC_IROWADDR	0x08		/* inital row address */
#define CRTC_MAXROW	0x09		/* maximum row address */
#define CRTC_CURSTART	0x0A		/* cursor start row address */
#define 	CURSOR_ON_BIT 0x20	/* cursor on/off on mda/cga/vga */
#define CRTC_CUREND	0x0B		/* cursor end row address */
#define CRTC_STARTADRH	0x0C		/* linear start address mid */
#define CRTC_STARTADRL	0x0D		/* linear start address low */
#define CRTC_CURSORH	0x0E		/* cursor address mid */
#define CRTC_CURSORL	0x0F		/* cursor address low */
#define CRTC_VSYNCS	0x10		/* vertical sync start */
#define CRTC_VSYNCE	0x11		/* vertical sync end */
#define CRTC_VDE	0x12		/* vertical display end */
#define CRTC_OFFSET	0x13		/* row offset */
#define CRTC_ULOC	0x14		/* underline row address */
#define CRTC_VBSTART	0x15		/* vertical blank start */
#define CRTC_VBEND	0x16		/* vertical blank end */
#define CRTC_MODE	0x17		/* CRTC mode register */
#define CRTC_SPLITL	0x18		/* split screen start low */

/* start of ET4000 extensions */

#define CRTC_RASCAS	0x32		/* ras/cas configuration */
#define CRTC_EXTSTART	0x33		/* extended start address */
#define CRTC_COMPAT6845	0x34		/* 6845 comatibility control */
#define CRTC_OVFLHIGH	0x35		/* overflow high */
#define CRTC_SYSCONF1	0x36		/* video system configuration 1 */
#define CRTC_SYSCONF2	0x36		/* video system configuration 2 */

/* start of WD/Paradise extensions */

#define	CRTC_PR10	0x29		/* r/w unlocking */
#define	CRTC_PR11	0x2A		/* ega switches */
#define	CRTC_PR12	0x2B		/* scratch pad */
#define	CRTC_PR13	0x2C		/* interlace h/2 start */
#define	CRTC_PR14	0x2D		/* interlace h/2 end */
#define	CRTC_PR15	0x2E		/* misc control #1 */
#define	CRTC_PR16	0x2F		/* misc control #2 */
#define	CRTC_PR17	0x30		/* misc control #3 */
					/* 0x31 .. 0x3f reserved */
/* Video 7 */

#define CRTC_V7ID	0x1f		/* identification register */

/* Trident */

#define CRTC_MTEST	0x1e		/* module test register */
#define CRTC_SOFTPROG	0x1f		/* software programming */
#define CRTC_LATCHRDB	0x22		/* latch read back register */
#define CRTC_ATTRSRDB	0x24		/* attribute state read back register*/
#define CRTC_ATTRIRDB	0x26		/* attribute index read back register*/
#define CRTC_HOSTAR	0x27		/* high order start address register */

/*---------------------------------------------------------------------------*
 *	VGA TIMING & SEQUENCER Registers			 (3C4 and 3C5)
 *---------------------------------------------------------------------------*/

#define TS_INDEX	0x3C4		/* index register */
#define TS_DATA		0x3C5		/* data register */

#define TS_SYNCRESET	0x00		/* synchronous reset */
#define TS_MODE		0x01		/* ts mode register */
#define TS_WRPLMASK	0x02		/* write plane mask */
#define TS_FONTSEL	0x03		/* font select register */
#define TS_MEMMODE	0x04		/* memory mode register */

/* ET4000 only */

#define TS_RESERVED	0x05		/* undef, reserved */
#define TS_STATECNTL	0x06		/* state control register */
#define TS_AUXMODE	0x07		/* auxiliary mode control */

/* WD/Paradise only */

#define TS_UNLOCKSEQ	0x06		/* PR20 - unlock sequencer register */
#define TS_DISCFSTAT	0x07		/* PR21 - display config status */
#define TS_MEMFIFOCTL	0x10		/* PR30 - memory i/f & fifo control */
#define TS_SYSIFCNTL	0x11		/* PR31 - system interface control */
#define TS_MISC4	0x12		/* PR32 - misc control #4 */

/* Video 7 */

#define TS_EXTCNTL	0x06		/* extensions control */
#define TS_CLRVDISP	0x30		/* clear vertical display 0x30-0x3f */
#define TS_V7CHIPREV	0x8e		/* chipset revision 0x8e-0x8f */
#define TS_SWBANK	0xe8		/* single/write bank register, rev 5+*/
#define TS_RDBANK	0xe8		/* read bank register, rev 4+ */
#define TS_MISCCNTL	0xe8		/* misc control register, rev 4+ */
#define TS_SWSTROBE	0xea		/* switch strobe */
#define TS_MWRCNTL	0xf3		/* masked write control */
#define TS_MWRMVRAM	0xf4		/* masked write mask VRAM only */
#define TS_BANKSEL	0xf6		/* bank select */
#define TS_SWREADB	0xf7		/* switch readback */
#define TS_PAGESEL	0xf9		/* page select */
#define TS_COMPAT	0xfc		/* compatibility control */
#define TS_16BITCTL	0xff		/* 16 bit interface control */

/* Trident */

#define TS_HWVERS	0x0b		/* hardware version, switch old/new! */
#define TS_CONFPORT1	0x0c		/* config port 1 and 2    - caution! */
#define TS_MODEC2	0x0d		/* old/new mode control 2 - caution! */
#define TS_MODEC1	0x0e		/* old/new mode control 1 - caution! */
#define	TS_PUPM2	0x0f		/* power up mode 2 */

/*---------------------------------------------------------------------------*
 *	VGA GRAPHICS DATA CONTROLLER Registers		    (3CE, 3CF and 3CD)
 *---------------------------------------------------------------------------*/

#define GDC_SEGSEL	0x3CD		/* segment select register */
#define GDC_INDEX	0x3CE		/* index register */
#define GDC_DATA	0x3CF		/* data register */

#define GDC_SETRES	0x00		/* set / reset bits */
#define GDC_ENSETRES	0x01		/* enable set / reset */
#define GDC_COLORCOMP	0x02		/* color compare register */
#define GDC_ROTFUNC	0x03		/* data rotate / function select */
#define GDC_RDPLANESEL	0x04		/* read plane select */
#define GDC_MODE	0x05		/* gdc mode register */
#define GDC_MISC	0x06		/* gdc misc register */
#define GDC_COLORCARE	0x07		/* color care register */
#define GDC_BITMASK	0x08		/* bit mask register */

/* WD/Paradise only */

#define GDC_BANKSWA	0x09		/* PR0A - bank switch a */
#define GDC_BANKSWB	0x0a		/* PR0B - bank switch b */
#define GDC_MEMSIZE	0x0b		/* PR1 memory size */
#define GDC_VIDEOSEL	0x0c		/* PR2 video configuration */
#define GDC_CRTCNTL	0x0d		/* PR3 crt address control */
#define GDC_VIDEOCNTL	0x0e		/* PR4 video control */
#define GDC_PR5GPLOCK	0x0f		/* PR5 gp status and lock */

/* Video 7 */

#define GDC_DATALATCH	0x22		/* gdc data latch */

/*---------------------------------------------------------------------------*
 *	VGA ATTRIBUTE CONTROLLER Registers			 (3C0 and 3C1)
 *---------------------------------------------------------------------------*/

#define ATC_INDEX	0x3C0		/* index register  AND	*/
#define ATC_DATAW	0x3C0		/* data write	   !!!	*/
#define ATC_DATAR	0x3C1		/* data read */

#define ATC_ACCESS	0x20		/* access bit in ATC index register */

#define ATC_PALETTE0	0x00		/* color palette register 0 */
#define ATC_PALETTE1	0x01		/* color palette register 1 */
#define ATC_PALETTE2	0x02		/* color palette register 2 */
#define ATC_PALETTE3	0x03		/* color palette register 3 */
#define ATC_PALETTE4	0x04		/* color palette register 4 */
#define ATC_PALETTE5	0x05		/* color palette register 5 */
#define ATC_PALETTE6	0x06		/* color palette register 6 */
#define ATC_PALETTE7	0x07		/* color palette register 7 */
#define ATC_PALETTE8	0x08		/* color palette register 8 */
#define ATC_PALETTE9	0x09		/* color palette register 9 */
#define ATC_PALETTEA	0x0A		/* color palette register 10 */
#define ATC_PALETTEB	0x0B		/* color palette register 11 */
#define ATC_PALETTEC	0x0C		/* color palette register 12 */
#define ATC_PALETTED	0x0D		/* color palette register 13 */
#define ATC_PALETTEE	0x0E		/* color palette register 14 */
#define ATC_PALETTEF	0x0F		/* color palette register 15 */
#define ATC_MODE	0x10		/* atc mode register */
#define ATC_OVERSCAN	0x11		/* overscan register */
#define ATC_COLPLEN	0x12		/* color plane enable register */
#define ATC_HORPIXPAN	0x13		/* horizontal pixel panning */
#define ATC_COLRESET	0x14		/* color reset */
#define ATC_MISC	0x16		/* misc register (ET3000/ET4000) */

/*---------------------------------------------------------------------------*
 *	VGA palette handling (output DAC palette)
 *---------------------------------------------------------------------------*/

#define VGA_DAC		0x3C6		/* vga dac address */
#define VGA_PMSK	0x3F		/* palette mask, 64 distinct values */
#define NVGAPEL 	256		/* number of palette entries */

/*---------------------------------------------------------------------------*
 *	function key labels
 *---------------------------------------------------------------------------*/

#define LABEL_LEN	9		/* length of one label */
#define LABEL_MID	8		/* mid-part (row/col)	*/

#define LABEL_ROWH	((4*LABEL_LEN)+1)
#define LABEL_ROWL	((4*LABEL_LEN)+2)
#define LABEL_COLU	((4*LABEL_LEN)+4)
#define LABEL_COLH	((4*LABEL_LEN)+5)
#define LABEL_COLL	((4*LABEL_LEN)+6)

/* tab setting */

#define MAXTAB 132		/* no of possible tab stops */

/* escape detection state machine */

#define STATE_INIT	0	/* normal	*/
#define	STATE_ESC	1	/* got ESC	*/
#define STATE_BLANK	2	/* got ESC space*/
#define STATE_HASH	3	/* got ESC #	*/
#define STATE_BROPN	4	/* got ESC (	*/
#define STATE_BRCLO	5	/* got ESC )	*/
#define STATE_CSI	6	/* got ESC [	*/
#define STATE_CSIQM	7	/* got ESC [ ?	*/
#define STATE_AMPSND	8	/* got ESC &	*/
#define STATE_STAR	9	/* got ESC *	*/
#define STATE_PLUS	10	/* got ESC +	*/
#define STATE_DCS	11	/* got ESC P	*/
#define STATE_SCA	12	/* got ESC <Ps> " */
#define STATE_STR	13	/* got ESC !	*/
#define STATE_MINUS	14	/* got ESC -	*/
#define STATE_DOT	15	/* got ESC .	*/
#define STATE_SLASH	16	/* got ESC /	*/

/* for storing escape sequence parameters */

#define MAXPARMS 	10	/* maximum no of parms */

/* terminal responses */

#define DA_VT220	"\033[?62;1;2;6;7;8;9c"

/* sub-states for Device Control String processing */

#define DCS_INIT	0	/* got ESC P ... */
#define DCS_AND_UDK	1	/* got ESC P ... | */
#define DCS_UDK_DEF	2	/* got ESC P ... | fnckey / */
#define DCS_UDK_ESC	3	/* got ESC P ... | fnckey / ... ESC */
#define DCS_DLD_DSCS	4	/* got ESC P ... { */
#define DCS_DLD_DEF	5	/* got ESC P ... { dscs */
#define DCS_DLD_ESC	6	/* got ESC P ... { dscs ... / ... ESC */

/* vt220 user defined keys and vt220 downloadable charset */

#define MAXUDKDEF	300	/* max 256 char + 1 '\0' + space.. */
#define	MAXUDKEYS	18	/* plus holes .. */
#define DSCS_LENGTH	3	/* descriptor length */
#define MAXSIXEL	8	/* sixels forever ! */

/* sub-states for HP-terminal emulator */

#define SHP_INIT	0

/* esc & f family */

#define SHP_AND_F	1
#define SHP_AND_Fa	2
#define SHP_AND_Fak	3
#define SHP_AND_Fak1	4
#define SHP_AND_Fakd	5
#define SHP_AND_FakdL	6
#define SHP_AND_FakdLl	7
#define SHP_AND_FakdLls	8

/* esc & j family */

#define SHP_AND_J	9
#define SHP_AND_JL	10

/* esc & every-thing-else */

#define SHP_AND_ETE	11

/* additionals for function key labels */

#define MAX_LABEL	16
#define MAX_STRING	80
#define MAX_STATUS	160

/* MAX values for screen sizes for possible video adaptors */

#define MAXROW_MDACGA	25		/* MDA/CGA can do 25 x 80 max */
#define MAXCOL_MDACGA	80

#define MAXROW_EGA	43		/* EGA can do 43 x 80 max */
#define MAXCOL_EGA	80

#define MAXROW_VGA	50		/* VGA can do 50 x 80 max */
#define MAXCOL_VGA	80
#define MAXCOL_SVGA	132		/* Super VGA can do 50 x 132 max */

/* switch 80/132 columns */

#define SCR_COL80	80		/* in 80 col mode */
#define SCR_COL132	132		/* in 132 col mode */

#define MAXDECSCA	(((MAXCOL_SVGA * MAXROW_VGA) \
			/ (8 * sizeof(unsigned int)) ) + 1 )

/* screen memory start, monochrome */

#ifndef	MONO_BUF
# if PCVT_FREEBSD && (PCVT_FREEBSD > 102)
#  define MONO_BUF	(KERNBASE+0xB0000)
# else
#  define MONO_BUF	0xfe0B0000		 /* NetBSD-current: isa.h */
# endif
#endif

/* screen memory start, color */

#ifndef	CGA_BUF
# if PCVT_FREEBSD && (PCVT_FREEBSD > 102)
#  define CGA_BUF	(KERNBASE+0xB8000)
# else
#  define CGA_BUF	0xfe0B8000		 /* NetBSD-current: isa.h */
# endif
#endif

#define	CHR		2		/* bytes per word in screen mem */

#define NVGAFONTS	8		/* number of vga fonts loadable */

#define MAXKEYNUM	127		/* max no of keys in table */

/* charset tables */

#define	CSL	0x0000		/* ega/vga charset, lower half of 512 */